Abstract: A data storage apparatus includes a nonvolatile memory device including block groups, a random access memory including a sequential map table that stores a sequential map entry for consecutive sequential write logical addresses, among write addresses received from a host apparatus, greater than or equal to a predetermined threshold number, and a processor configured to determine whether or not first sequential write logical addresses are present among logical addresses corresponding to physical addresses for a first region of a first block group when a write operation for the first region of the first block group in response to a write request received from the host apparatus is completed, generate a first sequential map entry for the first sequential write logical addresses when the first sequential write logical addresses are present, and store the first sequential map entry in the sequential map table.

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Abstract: A cache controller is to allocate memory within set-associative cache that includes a plurality of sets of ways. The cache controller is to request to assign an entry for a system address in the set-associative cache and execute a function to determine a set, from a series of sets within the plurality of sets of ways, to which to allocate the entry in the set-associative cache. The cache controller is further to identify an available number of ways in the set and identify a way that is available in response to execution of a way bias algorithm. The cache controller is also to determine whether the way is among the ways available within the set and select the way for allocation of the entry in response to the way being among the ways available within the set.

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.

Abstract: A management apparatus, which is configured to manage at least one storage system, includes a processor and a memory. Each of the at least one storage apparatus includes a plurality of volumes, each of which stores at least one OS. The processor is configured to: determine, for each of the plurality of volumes, an OS type and version of a representative OS of the each of the plurality of volumes; select, from among the plurality of volumes, a plurality of volumes having representative OSes that share the same OS type and major version; and include the selected plurality of volumes in one deduplication group made up of volumes among which deduplication is to be executed.

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.

Abstract: Systems, apparatuses, and methods for generating flexibly addressed memory requests are disclosed. In one embodiment, a system includes a processor, control unit, and memory subsystem. The processor launches a plurality of threads on a plurality of compute units, wherein each thread generates memory requests without specifying target memory addresses. The threads executing on the plurality of compute units convey a plurality of memory requests to the control unit. The control unit generates target memory addresses for the plurality of received memory requests. In one embodiment, the memory requests are write requests, and the control unit interleaves write requests from the plurality of threads into a single output buffer stored in the memory subsystem. The control unit can be located in a cache, in a memory controller, or in another location within the system.

Abstract: Embodiments are directed to a method performed by a computing device. The method includes (a) receiving, by the computing device, a stream of storage management commands directed at logical disks hosted by a DSS, the logical disks being accessible to VMs running on a remote host, each storage management command having a command type of a plurality of command types, each command type of the plurality of command types having a respective timeout period, (b) placing the storage management commands of the stream into a VM storage management queue stored on the computing device, and (c) selectively dequeueing storage management commands stored in the VM storage management queue to be performed by the DSS, wherein selectively dequeueing includes applying a set of dequeueing criteria, the set of dequeueing criteria including a criterion that selects storage management commands from the VM storage management queue according to their respective command types.

Abstract: The present application is directed to employing intermediary structures for facilitating access to secure memory. A secure driver (SD) may be loaded into the device to reserve a least a section of memory in the device as a secure page cache (SPC). The SPC may protect application data from being accessed by other active applications in the device. Potential race conditions may be avoided through the use of a linear address manager (LAM) that maps linear addresses (LAs) in an application page table (PT) to page slots in the SPC. The SD may also facilitate error handling in the device by reconfiguring VEs that would otherwise be ignored by the OS.

Abstract: There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The memory block may include a plurality of pages arranged in a vertical direction on a substrate. The peripheral circuits may perform a program operation on a selected page. The control logic may control the peripheral circuits to perform a first partial program operation of sequentially programming some of the pages up to a first page. The control logic may perform a first partial erase operation of erasing the other non-programmed pages. The control logic may perform a second partial program operation of partially programming the pages on which the first partial erase operation has been performed.

Abstract: Determining cache value currency using persistent markers is disclosed herein. In one example, a cache entry is retrieved from a local cache memory device. The cache entry includes a key, a value to be used by the computing device, and a marker flag to determine whether the cache entry is current. The local cache memory device also includes a marker location that indicates a location of a marker in a shared persistent fabric-attached memory (FAM). Using a marker location, the marker is retrieved from the shared persistent FAM. From the marker and the marker flag, it is determined whether the cache entry is current. The shared FAM pool is connected to the local cache memory devices of multiple computing devices.

Abstract: A method is used in determining suitability of storage. Storage data of a data storage system is analyzed. The storage data includes information associated with use of a storage object of the data storage system by an application of the data storage system. A storage suitability characteristic for the storage object is determined. The storage suitability characteristic for the storage object is provided to a user for provisioning storage for the application in the data storage system.

Abstract: A system and method is described for managing mapping data in a non-volatile memory system having a volatile memory cache smaller than the update table for the mapping data. The system includes multiple mapping layers, for example two mapping layers, including a master mapping table of logical-to-physical mapping entries and an update table of mapping updates, for a non-volatile memory. A processor swaps predetermined size portions of the update mapping table and master mapping table into and out of the volatile memory cache based on host workload. The update mapping table portions may have a fixed or an adaptive logical range. Additional mapping layers, such as an expanded mapping layer having portions with a logical range greater than the logical range of the update mapping portions, may also be included and may be swapped into and out of the volatile memory with the master and update mapping table portions.

Abstract: Memory-mapped interfaces for message passing computing systems are provided. According to various embodiments, a write request is received. The write request comprises write data and a write address. The write address is a memory address within a memory map. The write address is translated into a neural network address. The neural network address identifies at least one input location of a destination neural network. The write data is sent via a network according to the neural network address to the at least one input location of the destination neural network. A message is received via the network from a source neural network. The message comprises data and at least one address. A location in a buffer is determined based on the at least one address. The data is stored at the location in the buffer. The buffer is accessible via the memory map.

Abstract: A technique for overwriting compressed data tests whether new data compressed with a first compression procedure fits within spaces provided for previous data. If the compressed new data does not fit, the technique compresses the new data using a second compression procedure. Assuming the second compression procedure reduces the compressed size of the new data to fit the available space, the technique stores the new data in the same location as the previous data. In this manner, overwrites can be accommodated in place without the need to create new mapping metadata.

Abstract: Systems and methods for data storage management technology that enables a guest module of a virtual machine to indicate an order in which a host module should write data from physical memory to a secondary storage. An example method may comprise: identifying, by a processing device executing a host module, a plurality of modifications to direct access excited (DAX) memory made by a plurality of direct access operations executed by a guest module of a virtual machine; determining, by the host module, an order of the plurality of modifications to DAX memory; receiving, by the host module, a synchronization request from the guest module; and responsive to the synchronization request, copying, by the host module, data from the DAX memory to a secondary storage in view of the order of the plurality of modifications.

Abstract: A computer program product, system, and method for determining one or more slices of a logical address space assigned to replication processor; determining an elapsed time since a start of a replication cycle; determining an expected number of slices that should have been replicated based on the elapsed time; and replicating one or more slices of the logical address space in response to determining the expected number of slices that should have been replicated is less than an actual number of slices replicated by the replication processor within the replication cycle.

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.