Abstract: Storage systems store data in a storage pool comprising storage devices or virtual devices. The storage pool may be allocated for a particular purpose. If a virtual device within the storage pool needs to be repurposed, the virtual device is removed from the storage pool. Data is moved from the removed virtual device to one or more target virtual devices. Segments of the source virtual device being removed are copied to target virtual devices. Mapping tables associating source segments with target segments are stored. If the storage system receives a request to access data stored on a virtual device that is removed, the storage system processes the mapping tables to determine where the data is stored.

Abstract: A memory system includes a semiconductor memory device including a plurality of memory blocks, including a first block storing data and a second block storing backup data, a plurality of pins, and a controller configured to output a control signal to the semiconductor memory in accordance with the command. When the controller receives from outside of the memory system, a read command for the data in the first block, and the data in the first block are available, the controller is configured to transmit the data in the first block to the outside of the memory system. When the controller receives from outside of the memory system, a read command for the data in the first block, and the data in the first block are not available, the controller is configured to transmit the backup data in the second block to the outside of the memory system.

Abstract: A memory apparatus including a memory cell array, a register unit and a command generator is provided. The memory cell array includes a plurality of memory cells. The register unit is configured to record a plurality of user-defined information. The command generator receives a user-defined command and operates at least two memory operations on the memory cell array according to the received user-defined command and the user-defined information. The user-defined information is generated according to the at least two memory operations. Furthermore, an operating method of a memory apparatus is also provided.

Abstract: A method, computer program product, and computing system for defining a UIS layer within a storage management application, wherein the UIS layer is configured to perform operations including object management within a storage system. A System API layer is defined within the storage management application, wherein the System API layer is positioned beneath the UIS layer and is configured to perform operations including persistence object management within the storage system.

Abstract: Technologies for control and status register (CSR) access include a computing device that starts a firmware initialization phase. The firmware accesses a CSR at an abstract CSR address. The computing device determines whether an upper part of the CSR address matches a cached upper part of a previously accessed CSR address. If the upper parts do not match, the computing device converts the CSR address into a physical address and caches the upper part of the CSR address and the upper part of the physical address. If the upper parts match, the computing device combines a cached upper part of a previously accessed physical address with an offset of the CSR address. The upper part may include 20 bits and the lower part may include 12 bits. The physical address may be a PCIe address of the CSR added with an MMCFG base address. Other embodiments are described and claimed.

Abstract: Described are techniques for controlling I/O response time. It is determined whether a first observed I/O response time for a storage group exceeds I/O performance specified by a service level objective. If so, first processing may be performed to decrease I/O performance for the storage group. The first processing may include: for each I/O directed to the storage group that is received within a first subsequent time period, determining a first response time denoting an amount of time taken to service each I/O prior to returning a response for each I/O; determining whether the first response time for each I/O is less than a response time delay threshold; and if the first response time for each I/O is less than the response time delay threshold, applying a response time delay to each I/O prior to returning a response for each I/O.

Abstract: An amplification number may be input into a storage subsystem interface. A processor in a storage system may receive an original input/output (I/O) request from an application. The processor may determine, in response to the amplification number being input, to duplicate the original I/O request one or more times. The processor may generate one or more duplicate I/O requests of the original I/O request. The processor may store the original I/O request in a general address space in the storage subsystem. The processor may store the one or more duplicate I/O requests in a reserved address space in the storage subsystem. The processor may execute the original I/O request and the one or more duplicate requests.

Abstract: A computer-implemented method includes monitoring page allocations in a file system that includes encrypted files, determining if a page allocation request corresponds to an encrypted file, and balancing encrypted page allocations across a plurality of virtual memory pools in response to determining that the page allocation request corresponds to an encrypted file. In some embodiments, balancing encrypted page allocations across the plurality of virtual memory pools comprises determining a virtual memory pool having a lowest encrypted page count and allocating a page from the virtual memory pool having the lowest encrypted page count. A corresponding computer program product and computer system are also disclosed herein.

Abstract: The disclosed technology provides for a solid state device that adaptively determines, responsive to receipt of a write command, whether or not to partition one or more individual logical blocks of data between multiple pages of a flash storage device. According to one implementation, the partitioning (e.g., spanning) determination is based on read frequency characteristics and the internal error correction code rate of the data.

Abstract: There is disclosed a technique for use in managing multi-granularity flash translation layers in solid state drives. An SSD comprising a flash translation layer (FTL) table and flash memory space is provided. The FTL table is reconfigured into a plurality of multiple sub-tables, where a first sub-table has a first logical page size and a second sub-table has a second logical page size, the first logical page size being smaller than the second logical page size. The flash memory space is reconfigured into multiple flash memory sub-spaces. The first sub-table is mapped to the first flash memory sub-space the second sub-table is mapped to the second flash memory sub-space.

Abstract: According to an aspect of the present invention, there is a method, computer program product and/or system for storing data that performs the following operations (not necessarily in the following order): (i) receiving a request to migrate a data file from primary storage to secondary storage; (ii) invoking a primary data extraction function, registered by a user, to determine primary data for the data file; and (iii) inserting the primary data into a stub file.

Abstract: A data processing system 4 includes a translation lookaside buffer 6 storing mapping data entries 10 indicative of virtual-to-physical address mappings for different regions of physical addresses. A hint generator 20 coupled to the translation lookaside buffer 6 generates hint data in dependence upon the storage of mapping data entries within the translation lookaside buffer 6. The hint generator 20 tracks the loading of mapping data entries and the eviction of mapping data entries from the translation lookaside buffer 6. The hint data is supplied to a memory controller 8 which controls how data corresponding to respective different regions of physical addresses is stored within a heterogeneous memory system, e.g. the power state of different portions of the memories storing different regions, which type of memory is used to store different regions.

Abstract: There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The memory block may include a plurality of pages arranged in a vertical direction on a substrate. The peripheral circuits may perform a program operation on a selected page. The control logic may control the peripheral circuits to perform a first partial program operation of sequentially programming some of the pages up to a first page. The control logic may perform a first partial erase operation of erasing the other non-programmed pages. The control logic may perform a second partial program operation of partially programming the pages on which the first partial erase operation has been performed.

Abstract: A system for performing a data transaction between a memory and a master via a bus based on a strobe signal. The memory includes at least one memory bank having first and second cuts. The data transaction is either a read transaction or a write transaction. The system includes an input and output interface in communication with the master for receiving a data transaction request, an identifying unit that identifies a type of the data transaction, a control unit that selectively enables at least one of the first and second cuts based on the data transaction type, and a data processing unit that processes data to be read from or written to the enabled cut based on the data transaction type.

Abstract: A system and method is disclosed for reducing a physical size of a data file that includes a plurality of blocks in sequence with each block having a defined size with a starting position and an end position. According to one aspect, the method includes obtaining information relating to an occupied physical region of the data file, where the occupied physical region contains unused space and/or unused data, and determining positions of first and second boundaries of the occupied physical region of the data file relative to the plurality of blocks in the data file. Furthermore, the method includes equalizing the occupied physical region by adjusting the first and second boundaries of the occupied physical region of the data file and removing data between the start and end of the removal region to reduce the physical size of the data file.

Abstract: A memory controller receives first and second write transactions from a processor and stores write data in a memory. The memory controller includes an address comparison circuit, a buffer, a level control circuit, a command generator, and a control circuit. The address comparison circuit compares second and third addresses and outputs first and second write data when the second and third addresses are consecutive. The buffer stores the first and second write data and outputs buffered data based on a control signal. The level control circuit compares a size of the buffered data with a threshold size and the size of the buffer. The command generator causes a write transaction to be executed based on the comparison results, rather than having the processor initiate the transaction, which reduces the load on the processor, and the buffered write data is stored in the memory.

Abstract: The disclosure discloses a method and a device of information protection for a micro control unit (MCU) chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory; the flash controller is used to divide the user area into a first sub-area and a second sub-area; the method comprising: when the instruction bus accesses the user area, determining, whether the instruction bus accesses the first sub-area; if yes, entering the first sub-area working state; in the first sub-area working state, if the instruction bus accesses the second sub-area, entering the transition state; determining whether the time at transition state reaches a preset waiting time; if yes, entering the second sub-area working state; the disclosure is used to protect program from being stolen by users and prevent the cooperative companies stealing program from each other.

Abstract: Solid state drives may include a controller, a mapping table and a buffer memory. The controller provides a logical address of associated data through a first input-output unit at a first speed and provides the associated data through a second input-output unit at a second speed. The controller may be connected to the first input-output unit and the second input-output unit. The mapping table may be connected to the controller through the first input-output unit. The buffer memory may be connected to the controller through the second input-output unit. The first input-output unit may be physically separated from the second input-output unit. The first speed may be different from the second speed.

Abstract: Method and apparatus for managing memory is disclosed herein. In one embodiment, the method includes specifying a first load-monitored region within a memory, configuring a performance monitor to count object pointer accessed events associated with the first load-monitored region, executing a CPU instruction to load a pointer that points to a first location in the memory, responsive to determining that the first location is within the first load-monitored region, triggering an object pointer accessed event, updating a count of object pointer accessed events in the performance monitor, and performing garbage collection on the first load-monitored region based on the count of object pointer accessed events.

Abstract: Method and apparatus for managing memory is disclosed herein. In one embodiment, the method includes specifying a first load-monitored region within a memory, configuring a performance monitor to count object pointer accessed events associated with the first load-monitored region, executing a CPU instruction to load a pointer that points to a first location in the memory, responsive to determining that the first location is within the first load-monitored region, triggering an object pointer accessed event, updating a count of object pointer accessed events in the performance monitor, and performing garbage collection on the first load-monitored region based on the count of object pointer accessed events.