Abstract: A leadframe with pre-molded cavities includes an outer frame and a plurality of units. Each unit includes a die pad and a plurality of leads. For each unit, a molding compound extends over a first portion of an upper surface of each of the leads that is located farthest from the die pad. The molding compound may also extend over an upper surface of the die pad. A second portion of the upper surface of each of the plurality of leads that is located nearest the die pad remains exposed outside the molding compound. A thickness of the molding compound covering the first portion of the upper surface of each of the leads is greater than a thickness of the molding compound covering the upper surface of the die pad.

Abstract: Semiconductor devices packages and methods are disclosed. In one embodiment, a package for a semiconductor device includes a substrate and a contact pad disposed on a first surface of the substrate. The contact pad has a first side and a second side opposite the first side. A conductive trace is coupled to the first side of the contact pad, and an extension of the conductive trace is coupled to the second side of the contact pad. A plurality of bond pads is disposed on a second surface of the substrate.

Abstract: A semiconductor wafer has a plurality of semiconductor die. First and second conductive layers are formed over opposing surfaces of the semiconductor die, respectively. Each semiconductor die constitutes a WLCSP. A TSV is formed through the WLCSP. A semiconductor component is mounted to the WLCSP. The first semiconductor component is electrically connected to the first conductive layer. A first bump is formed over the first conductive layer, and a second bump is formed over the second conductive layer. An encapsulant is deposited over the first bump and first semiconductor component. A second semiconductor component is mounted to the first bump. The second semiconductor component is electrically connected to the first semiconductor component and WLCSP through the first bump and TSV. A third semiconductor component is mounted to the first semiconductor component, and a fourth semiconductor component is mounted to the third semiconductor component.

Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

Abstract: A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Abstract: Composite heat sink structures and methods of fabrication are provided, with the composite heat sink structures including: a thermally conductive base having a main heat transfer surface to couple to, for instance, at least one electronic component to be cooled; a compressible, continuous sealing member; and a sealing member retainer compressing the compressible, continuous sealing member against the thermally conductive base; and an in situ molded member. The in situ molded member is molded over and affixed to the thermally conductive base, and is molded over and secures in place the sealing member retainer. A coolant-carrying compartment resides between the thermally conductive base and the in situ molded member, and a coolant inlet and outlet are provided in fluid communication with the coolant-carrying compartment to facilitate liquid coolant flow through the compartment.

Abstract: A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.

Abstract: An object of an embodiment of the present invention is to provide a semiconductor device including a normally-off oxide semiconductor element whose characteristic variation is small in the long term. A cation containing one or more elements selected from oxygen and halogen is added to an oxide semiconductor layer, thereby suppressing elimination of oxygen, reducing hydrogen, or suppressing movement of hydrogen. Accordingly, carriers in the oxide semiconductor can be reduced and the number of the carriers can be kept constant in the long term. As a result, the semiconductor device including the normally-off oxide semiconductor element whose characteristic variation is small in the long term can be provided.

Abstract: System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid interconnect may have a predetermined length configured to provide a predetermined package separation, may be cylindrical, conical or stepped, may be formed by extrusion, casting, drawing or milling and may have an anti-oxidation coating. The interconnect may be attached to mounting pads on the top and bottom packages via an electrically conductive adhesive, including, but not limited to solder and solder paste. A solder preservative or other anti-oxidation coating may be applied to the mounting pad. A package-on-package assembly with solid interconnects may have a top package configured to accept at least one electronic device, with the solid interconnects mounted between the top package and a bottom package to rigidly hold the package about parallel to each other.

Abstract: Composite heat sink structures and methods of fabrication are provided, with the composite heat sink structures including: a thermally conductive base having a main heat transfer surface to couple to, for instance, at least one electronic component to be cooled; a compressible, continuous sealing member; and a sealing member retainer compressing the compressible, continuous sealing member against the thermally conductive base; and an in situ molded member. The in situ molded member is molded over and affixed to the thermally conductive base, and is molded over and secures in place the sealing member retainer. A coolant-carrying compartment resides between the thermally conductive base and the in situ molded member, and a coolant inlet and outlet are provided in fluid communication with the coolant-carrying compartment to facilitate liquid coolant flow through the compartment.

Abstract: A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.

Abstract: A method of forming a wafer stack includes providing a sub-stack comprising a first wafer and a second wafer. The sub-stack includes a first thermally-curable adhesive at an interface between the upper surface of the first wafer and the lower surface of the second wafer. A third wafer is placed on the upper surface of the second wafer. A second thermally-curable adhesive is present at an interface between the upper surface of the second wafer and the lower surface of the third wafer. Ultra-violet (UV) radiation is provided in a direction of the upper surface of the third wafer to cure a UV-curable adhesive in openings in the second wafer and in contact with portions of the third wafer so as to bond the third wafer to the sub-stack at discrete locations. Subsequently, the third wafer and the sub-stack are heated so to cure the first and second thermally-curable adhesives.

Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

Abstract: The invention relates to a chip arrangement (18) comprising a terminal substrate (12) and a plurality of semiconductor substrates (1) which are arranged on the terminal substrate, in particular chips, wherein terminal faces (5) arranged on a contact surface of the chips (1) are connected to terminal faces on a contact surface (14) of the terminal substrate (12), wherein the chips (1) extend parallel with a lateral edge and transversally with their contact surface to the contact surface of the terminal substrate (12), wherein vias (13) are arranged in the terminal substrate, which connect external contacts (15) arranged on an external contact side to terminal faces formed as internal contacts (14) on the contact surface of the terminal substrate, wherein terminal faces of the chips, which are arranged adjacent to the lateral edge, are connected to the internal contacts of the terminal substrate by way of a re-melted solder material deposit (16).

Abstract: A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.

Abstract: Included are: the third frame which is electrically connected to the first intermediate frame and is arranged above the first frame; the fourth frame which is electrically connected to the second intermediate frame and is arranged above the second frame; the electric source terminal part which is provided on an extension of the first frame; the ground terminal part which is provided on an extension of the fourth frame; and the output terminal part which is provided on an extension to which the second frame and the third frame are electrically joined, wherein the third frame and the fourth frame are arranged in parallel with each other, and the electric source terminal part, the ground terminal part and the output terminal part are arranged in a manner such that induced electric voltages, which are generated in the third frame and the fourth frame, become in reverse directions with each other.

Abstract: Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads.

Abstract: An object of an embodiment of the present invention is to provide a semiconductor device including a normally-off oxide semiconductor element whose characteristic variation is small in the long term. A cation containing one or more elements selected from oxygen and halogen is added to an oxide semiconductor layer, thereby suppressing elimination of oxygen, reducing hydrogen, or suppressing movement of hydrogen. Accordingly, carriers in the oxide semiconductor can be reduced and the number of the carriers can be kept constant in the long term. As a result, the semiconductor device including the normally-off oxide semiconductor element whose characteristic variation is small in the long term can be provided.

Abstract: A semiconductor device may include an IC, and lead frame contact areas adjacent the IC. Each lead frame contact area may have a lead opening. The semiconductor device may include bond wires, each bond wire coupling a respective lead frame contact area with the IC. The semiconductor device may include encapsulation material surrounding the IC, the lead frame contact areas, and the bond wires, and leads. Each lead may extend through a respective lead opening and outwardly from the encapsulation material.