Patents Examined by Abdulfattah Mustapha
  • Patent number: 10446081
    Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a lower substrate including a display area and a non-display area surrounding the display area, wherein a plurality of pixels are formed in the display area. The OLED display also includes an embedded circuit formed in the configured to apply a plurality of signals to the pixels, and an initialization wiring formed in the non-display area and configured to apply an initialization voltage to each of the pixels. The initialization circuit is formed in a layer so as to at least partially overlap with the area of the embedded circuit.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Chang-Soo Pyon
  • Patent number: 10326020
    Abstract: Various methods and structures for fabricating a strained semiconductor fin of a FinFET device. A strained semiconductor fin structure includes a substrate, a semiconductor fin disposed on the substrate, the semiconductor fin having two fin ends, and a stressor material cladding wrapped around a portion of each of the two fin ends forming a strained semiconductor fin that includes at least one strained channel fin having stressor cladding wrapped around at least one end of the strained channel fin thereby straining the at least one strained channel fin. The stressor cladding can be a compressive nitride stressor to compressively strain a compressively strained silicon germanium fin. The stressor cladding can be a tensile nitride stressor to tensily strain a tensily strained silicon fin.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li
  • Patent number: 10312134
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: June 4, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Qingmin Liu
  • Patent number: 10283638
    Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack comprises a plurality of sacrificial layers in which each sacrificial layer comprises a first lattice parameter; and at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter and in which each channel layer is disposed between and in contact with two sacrificial layers. The stack is formed on an underlayer in which a sacrificial layer is in contact with the underlayer. The underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 7, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jorge A. Kittl, Ganesh Hegde, Robert C. Bowen, Mark S. Rodder
  • Patent number: 10249791
    Abstract: A high-brightness light-emitting diode with surface microstructure and preparation and screening methods thereof are provided. The ratio of total roughened surface area of light transmission surface of a light emitting diode to vertically projected area is greater than 1.5, and the peak density of light transmission surface is not less than 0.3/um2. The higher the ratio of total roughened surface area of an epitaxial wafer to vertically projected area and the higher the number of peak over the critical height within a unit area, the more beneficial to improve light extraction efficiency of the epitaxial wafer. As a result, light extraction efficiency of the epitaxial wafer is greatly improved.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: April 2, 2019
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Chaoyu Wu, Kunhuang Cai, Yi-An Lu, Chun-Yi Wu, Ching-Shan Tao, Duxiang Wang
  • Patent number: 10211240
    Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 10205074
    Abstract: A semiconductor light emitting device package includes a semiconductor light emitting device including a plurality of electrodes, a circuit board including a mounting region, the semiconductor light emitting device being positioned on the mounting region of the circuit board, and a plurality of electrode pads on the circuit board, the plurality of electrode pads being electrically connected to the plurality of electrodes, wherein each of the plurality of electrode pads includes a first region and a second region, the first region overlapping the mounting region, and the second region excluding the first region, and wherein the plurality of electrode pads is arranged in a shape of rotational symmetry around a pivot point of the mounting region.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong Sup Song
  • Patent number: 10186452
    Abstract: An asymmetric stair structure includes multiple unit layers and has m regions (m?2). In each of the m regions, a different part of unit layers having an interval of m unit layers each have a portion not covered by an upper adjacent unit layer, so that a stair having a step difference of m unit layers is formed. In arbitrary two of the m regions, the two different parts of unit layers include no repeated unit layers.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 22, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Yao-Yuan Chang
  • Patent number: 10170616
    Abstract: One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Steven J. Bentley, Jody A. Fronheiser
  • Patent number: 10170554
    Abstract: A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate structure; and a protection layer between the substrate and the raised source/drain region. The protection layer is interposed between the substrate and the raised source/drain region. An atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Jia Hsieh, Hsin-Hung Chen, Yi-Chun Lo, Jung-You Chen
  • Patent number: 10167544
    Abstract: There are provided a vapor deposition mask capable of satisfying both high definition and lightweight in upsizing and forming a vapor deposition pattern with high definition while securing strength, a vapor deposition mask preparation body capable of simply producing the vapor deposition mask and a method for producing a vapor deposition mask, and furthermore, a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition. A metal mask 10 in which a slit 15 is provided and a resin mask 20 in which openings 25 corresponding to a pattern to be produced by vapor deposition are provided at a position of overlapping with the slit 15 are stacked, and the metal mask 10 has a general region 10a in which the slit 15 is provided and a thick region 10b larger in thickness than the general region.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: January 1, 2019
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Katsunari Obata, Toshihiko Takeda, Hiroshi Kawasaki, Hiroyuki Nishimura, Atsushi Maki, Hiromitsu Ochiai, Yoshinori Hirobe
  • Patent number: 10166632
    Abstract: A method for aligning a scan laser beam on a wafer include scanning a scan laser beam across a laser beam sensor along a scan line, picking up a scan laser beam, at a first position, using a first optical slit of the laser beam sensor to generate a first electrical pulse, picking up the scan laser beam, at a second position, using a second optical slit of the laser beam sensor to generate a second electrical pulse, picking up the scan laser beam, at a third position, using a third optical slit of the laser beam sensor to generate a third electrical pulse, and determining a spot size and a position of the laser beam based on the first to third electrical pulses.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Russell Budd, Robert Polastre, Paul Andry
  • Patent number: 10170484
    Abstract: In a method of forming a structure with field effect transistors (FETs) having different drive currents, a stack is formed on a substrate. The substrate is a first semiconductor material and the stack includes alternating layers of a second and the first semiconductor material. Recess(es) filled with sacrificial material are formed in certain area(s) of the stack. The stack is patterned into fins and gate-all-around (GAA) FET processing is performed. GAAFET processing includes removing sacrificial gates to form gate openings for GAAFETs and removing the second semiconductor material and any sacrificial material (if present) from the gate openings such that, within each gate opening, nanoshape(s) that extend laterally between source/drain regions remain. Gate openings for GAAFETs where sacrificial material was removed will have fewer nanoshapes than other gate openings. Thus, in the structure, some GAAFETs will have fewer channel regions and, thereby lower drive currents than others.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Ruilong Xie, Bipul C. Paul
  • Patent number: 10147640
    Abstract: A method for preparing a porous dielectric is described. In particular, the method includes removing pore-filling agent from pores in a cured porous dielectric layer, wherein the pore-filling agent was back-filled within the pores following the removal of a pore-forming agent during a curing process. The removal of the pore-filling agent includes heating a substrate holder upon which the substrate rests to a holder temperature greater than 100 degrees C. and less than 400 degrees C., and while heating the substrate holder, exposing the substrate to electromagnetic (EM) radiation, wherein the EM radiation includes emission at a wavelengths within the ultraviolet (UV) spectrum, visible spectrum, infrared (IR) spectrum, or microwave spectrum, or combination thereof.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: December 4, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Junjun Liu
  • Patent number: 10141054
    Abstract: A semiconductor device that has a long data retention time during stop of supply of power supply voltage by reducing leakage current due to miniaturization of a semiconductor element. In a structure where charge corresponding to data is held with the use of low off-state current of a transistor containing an oxide semiconductor in its channel formation region, a transistor for reading data and a transistor for storing charge are separately provided, thereby decreasing leakage current flowing through a gate insulating film.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Munehiro Kozuma, Yoshiyuki Kurokawa
  • Patent number: 10134747
    Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: November 20, 2018
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10128238
    Abstract: A method includes epitaxially depositing source/drains on parallel semiconductor fins having parallel polysilicon gate precursor structures disposed thereon orthogonally to the fins, where two adjacent polysilicon gate precursor structures are joined together and connected at ends thereof by a polysilicon loop portion. The method further includes oxidizing the ends of the polysilicon precursor gate structures, the connecting polysilicon loop portion and any semiconductor nodules that formed on the connecting polysilicon loop portion during the step of epitaxially depositing the source/drains. A structure includes a substrate; a plurality of parallel semiconductor fins disposed on the substrate; a plurality of parallel metal gate structures overlying the plurality of fins and orthogonal to the plurality of fins; and a plurality of source/drain structures disposed on the fins.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Andrew Mark Greene, Peng Xu
  • Patent number: 10115759
    Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor includes a device isolation layer provided in a trench of a substrate, the device isolation layer defining a pixel; and a photoelectric conversion device provided in the pixel. The device isolation layer includes a conductive layer, a tunneling layer interposed between the conductive layer and the substrate, and a trap layer interposed between the tunneling layer and the conductive layer.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: October 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngbin Lee, GukHyon Yon, Soojin Hong
  • Patent number: 10101621
    Abstract: A display substrate and a display device are provided. The display substrate includes: plural gate lines each having at least one end provided with plural first electrostatic discharge (ESD) units configured to discharge static electricity in the gate lines. The plural first ESD units have curvatures different from each other. By discharging the static electricity through the plural ESD units, in case one of the ESD units is broken down by electrostatic current, the other ones can continue working.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: October 16, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE TECHNOLOGY CO., LTD.
    Inventors: Haichen Hu, Su Min, Jinwei Shi, Donghui Qi, Shuai Hou, Liping Luo, Zengbiao Sun, Tao Wang
  • Patent number: 10096478
    Abstract: The present invention for imaging sensor rejuvenation may include a rejuvenation illumination system configured to selectably illuminate a portion of an imaging sensor of an imaging system with illumination suitable for at least partially rejuvenating the imaging sensor degraded by exposure to at least one of extreme ultraviolet light or deep ultraviolet light; and a controller communicatively coupled to the rejuvenation illumination system and configured to direct the rejuvenation illumination system to illuminate the imaging sensor for one or more illumination cycles during a non-imaging state of the imaging sensor.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: October 9, 2018
    Assignee: KLA-Tencor Corporation
    Inventors: Gildardo Delgado, Gary Janik