Abstract: Methods of processing a substrate are provided herein. In some embodiments, a method of processing a substrate disposed in a processing chamber includes: (a) depositing a layer of material on a substrate by exposing the substrate to a first reactive species generated from a remote plasma source and to a first precursor, wherein the first reactive species reacts with the first precursor; and (b) treating all, or substantially all, of the deposited layer of material by exposing the substrate to a plasma generated within the processing chamber from a second plasma source; wherein at least one of the remote plasma source or the second plasma source is pulsed to control periods of depositing and periods of treating.

Abstract: According to one embodiment, a display device includes a first subpixel and a second subpixel. An area, in a plan view, surrounded by a first signal line, a second signal line, a first scanning line, and a second scanning line and including a first pixel electrode is a first area. An area, in a plan view, surrounded by the first signal line, the second signal line, the second scanning line, and a third scanning line and including a second pixel electrode is a second area. The first area has a first distance in the first direction and the second area has a second distance in the first direction. The first distance is greater than the second distance.

Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

Abstract: A photodiode pixel structure for imaging short wave infrared (SWIR) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (ROIC), for example, a silicon complementary metal-oxide-semiconductor (CMOS) circuit. The photodiode in each pixel is buried under the surface and does not directly contact the ROIC amplification circuit. Disconnecting the photodiode from the ROIC amplification circuit enables low dark current as well as double correlated sampling in the pixel.

Abstract: An object of the present invention is to provide an organic semiconductor composition, which makes it possible to obtain an organic semiconductor film having high mobility and being excellent in film uniformity and heat resistance, and a method for manufacturing an organic semiconductor element. The organic semiconductor composition of the present invention contains an organic semiconductor as Component A and an organic solvent, which is represented by Formula B-1 and has a melting point of equal to or lower than 25° C. and a boiling point of equal to or higher than 150° C. and equal to or lower than 280° C., as Component B, in which an ionization potential of Component A is equal to or higher than 5.1 eV. In the formula, X represents O, S, S?O, O?S?O, or NR, Y1 to Y4 each independently represent NR1 or CR10R11, R, R1, R10, and R11 each independently represent a hydrogen atom or a substituent, and n represents 1 or 2.

Abstract: A molded nanoparticle phosphor for light emitting applications is fabricated by converting a suspension of nanoparticles in a matrix material precursor into a molded nanoparticle phosphor. The matrix material can be any material in which the nanoparticles are dispersible and which is moldable. The molded nanoparticle phosphor can be formed from the matrix material precursor/nanoparticle suspension using any molding technique, such as polymerization molding, contact molding, extrusion molding, injection molding, for example. Once molded, the molded nanoparticle phosphor can be coated with a gas barrier material, for example, a polymer, metal oxide, metal nitride or a glass. The barrier-coated molded nanoparticle phosphor can be utilized in a light-emitting device, such as an LED. For example, the phosphor can be incorporated into the packaging of a standard solid state LED and used to down-convert a portion of the emission of the solid state LED emitter.

Abstract: Embodiments include a manufacturing method of making a semiconductor device via multiple stages of alignment bonding and substrate removal. One example is an integrated full-color LED display panel, in which multiple wafers with different arrays of LEDs are integrated onto a host wafer with driver circuitry. The driver circuitry typically is an array of pixel drivers that drive individual LEDs on the display panel.

Abstract: The invention relates to method for manufacturing an electronic device comprising an organic layer (120). According to this method, a stack with a metal layer (130) and an organic layer (120) as first and second outer layers is structured by etching both these outer layers. In one particular embodiment, an additional metal layer (140) may be generated on the outermost metal layer (130) by galvanic growth through a structured isolation 10 layer (150). After removal of said isolation layer (150), the metal (130) may be etched in the openings of the additional metal layer (140). In a further etching step, the organic material (120) may be removed in said openings, too.

Abstract: A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate structure having a gate insulation layer over the semiconductor layer and at least one P-type metal-oxide semiconductor gate structure being a PZG gate structure having a gate insulation layer over the semiconductor layer, the NZG and PZG gate structures being electrically separated from each other.

Abstract: Provided is an adhesive composition for multilayer semiconductors. The adhesive composition gives, when applied and dried by heating, an adhesive layer that has approximately no adhesiveness at a temperature lower than 50° C., but, when heated at such a temperature as to less cause damage to semiconductor chips, offers adhesiveness and is rapidly cured thereafter. This adhesive composition for multilayer semiconductors includes a polymerizable compound (A), at least one of a cationic-polymerization initiator (B1) and an anionic-polymerization initiator (B2), and a solvent (C). The polymerizable compound (A) contains 80% by weight or more of an epoxide having a softening point or melting point of 50° C. or higher. The cationic-polymerization initiator (B1) gives a composition having a thermal curing time of 3.5 minutes or longer at 130° C.

Abstract: A method of manufacturing a semiconductor device is provided. The device includes a substrate including a first type region and a second type region, first and second fins protruding from the substrate and separated by a trench. The first fin includes first and second portions of the first type on the first region and a third portion of the second type on the second region. A first gate structure surrounds the second portion and the third portion. A first work function adjusting layer is on the gate insulator layer on the first and second portions. A second work function adjusting layer is on the first work function adjusting layer, the gate insulator layer on the third portion, and the first insulator layer. The device also includes a gate on the second work function adjusting layer, a hardmask layer on the gate, and an interlayer dielectric layer surrounding the gate structure.

Abstract: A method of fabricating an organic photovoltaic device. The method includes providing a first electrode which by applying a layer of conductive material onto a transparent substrate. The conductive material forms the first electrode. The method also includes placing an active layer of organic photovoltaic material on top of the first electrode. The active layer is configured to convert photonic energy into electrical energy. Placing an active layer of organic photovoltaic material includes placing an active layer of organic photovoltaic material having ferroelectric dipoles dispersed therein. The method further includes applying a second electrode on top of the active layer of organic photovoltaic material.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.

Abstract: Methods of fabricating integrated circuits and integrated circuits fabricated by those methods are provided. In an exemplary embodiment, a method includes providing a substrate having a first and second device wells, a gate dielectric overlying the first and second device wells, a first gate electrode layer overlying the gate dielectric, and a shallow trench isolation structure between the first and second device wells. An insulating dielectric layer is formed only partially overlying the first gate electrode layer. A second gate electrode material is deposited overlying at least the insulating dielectric layer to form a second gate electrode layer. The layers are patterned to form a second gate structure overlying the second device well. A contact is formed on the second gate electrode layer of the second gate structure with the contact overlying dielectric material of at least one of the insulating dielectric layer or the shallow trench isolation structure.

Abstract: Provided is a method for manufacturing a composite body, the method containing: a composition preparation process of preparing a composition that contains a polymer having a cationic functional group and having a weight average molecular weight of from 2,000 to 1,000,000, and that has a pH of from 2.0 to 11.0; a composite member preparation process of preparing a composite member that includes a member A and a member B, a surface of the member B having a defined isoelectric point, and that satisfies a relationship: the isoelectric point of a surface of the member B< the pH of the composition<the isoelectric point of a surface of the member A; and an application process of applying the composition to the surface of the member A and the surface of the member B included in the composite member.

Abstract: In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.

Abstract: A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.

Abstract: In a soldering method for Ag-containing lead-free solders to be soldered to an Ag-containing member, void generation is prevented and solder wettability is improved. The soldering method for Ag-containing lead-free solders of the present invention is a soldering method for Ag-containing lead-free solders includes a first step of bringing a lead-free solder having a composition that contains Ag that a relation between a concentration C (mass %) of Ag contained in an Sn—Ag-based lead-free solder before soldering of a mass M(g) and an elution amount B(g) of Ag contained in the Ag-containing member becomes 1.0 mass %?(M×C+B)×100/(M+B)?4.6 mass % and that the balance consists of Sn and unavoidable impurities into contact with the Ag-containing member, a second step of heating and melting the lead-free solder, and a third step of cooling the lead-free solder.

Abstract: In a method according to embodiments of the invention, a III-nitride layer is grown on a growth substrate. The III-nitride layer is connected to a host substrate. The growth substrate is removed. The growth substrate is a non-III-nitride material. The growth substrate has an in-plane lattice constant asubstrate. The III-nitride layer has a bulk lattice constant alayer. In some embodiments, [(|asubstrate?alayer|)/asubstrate]*100% is no more than 1%.