Abstract: A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.

Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough.

Abstract: A photovoltaic device includes an intrinsic layer having two or more sublayers. The sublayers are intentionally deposited to include complementary concave and convex shapes. The sum of these layers resulting in a relatively flat surface for deposition of n- or p-doped layers. The photovoltaic device is optionally bifacial.

Abstract: Provided is a method of doping a substrate. The method includes providing the substrate, providing a target material on the substrate, and implanting a dopant of the target material into the substrate by providing a laser beam to the target material.

Abstract: A method of fabricating an organic photovoltaic device. The method includes providing a first electrode which by applying a layer of conductive material onto a transparent substrate. The conductive material forms the first electrode. The method also includes placing an active layer of organic photovoltaic material on top of the first electrode. The active layer is configured to convert photonic energy into electrical energy. Placing an active layer of organic photovoltaic material includes placing an active layer of organic photovoltaic material having ferroelectric dipoles dispersed therein. The method further includes applying a second electrode on top of the active layer of organic photovoltaic material.

Abstract: A laser annealing apparatus includes: a substrate supporting unit which supports a substrate; a laser beam irradiating unit which irradiates a line laser beam extending in a first direction to an amorphous silicon layer provided on the substrate on the substrate supporting unit; a substrate moving unit which moves the substrate supporting unit in a second direction crossing the first direction; and a first beam cutter and a second beam cutter, which are disposed between the substrate supporting unit and the laser beam irradiating unit, where the first and second beam cutters move to increase or decrease a shielded area of the substrate, which is an area of the substrate overlapping the first or second beam cutter and the line laser beam, to shield from at least a portion of the line laser beam irradiated to a portion of the substrate at an outer portion of the amorphous silicon layer.

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

Abstract: An OLED display includes pixels, each including a first light emission region having a first area and a first perimeter and a second light emission region disposed neighboring the first light emission region and having a second area and a second perimeter. The first area, the first perimeter, the second area, and the second perimeter respectively satisfy an equation of A1*P2=A2*P1, where A1 is the first area, P1 is the first perimeter, A2 is the second area, and P2 is the second perimeter.

Abstract: A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed, wherein: the shielded gate structure comprises a first poly-silicon layer to serve as a shielded electrode and a second poly-silicon layer to serve as a gate electrode, and the ESD clamp diode formed between two protruding electrodes is also formed by the first poly-silicon layer. A mask specially used to define the ESD clamp diode portion is saved.

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

Abstract: The present technology includes: bonding a device formation side of a first substrate having a first device and a device formation side of a second substrate having a second device in opposition to each other; forming a protective film on at least an edge of the second substrate having the second device; and reducing a thickness of the first substrate.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a lower substrate including a display area and a non-display area surrounding the display area, wherein a plurality of pixels are formed in the display area. The OLED display also includes an embedded circuit formed in the configured to apply a plurality of signals to the pixels, and an initialization wiring formed in the non-display area and configured to apply an initialization voltage to each of the pixels. The initialization circuit is formed in a layer so as to at least partially overlap with the area of the embedded circuit.

Abstract: A photodiode pixel structure for imaging short wave infrared (SWIR) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (ROIC), for example, a silicon complementary metal-oxide-semiconductor (CMOS) circuit. The photodiode in each pixel is buried under the surface and does not directly contact the ROIC amplification circuit. Charge is transferred form the detector using a junction field effect transistor (JFET) in each pixel. Disconnecting the photodiode from the ROIC amplification circuit enables low dark current as well as double correlated sampling in the pixel.

Abstract: A transient voltage suppressor can include: a semiconductor substrate; a first buried layer of a first type formed in and on the semiconductor substrate; a second buried layer of a second type formed in a first region of the first buried layer; a first epitaxial region of the second type formed on the second buried layer and a second epitaxial region of the first type formed on a second region of the first buried layer; a first doped region of the first type formed in the first epitaxial region and a second doped region of the second type formed in the second epitaxial region; a conductive channel extending from a surface of the second epitaxial region into the first buried layer; and a first electrode connected to the conductive channel, a second electrode connected to the first doped region, and a third electrode connected to the second doped region.

Abstract: This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface thereof, a supporting substrate, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in a furnace in which structures are supported on a support, the dissolution method resulting in the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products, and the furnace including traps suitable for reacting with the volatile products, so as to reduce the concentration gradient of the volatile products parallel to the front surface of at least one structure.

Abstract: An organic electroluminescence display panel includes a substrate, an organic light-emitting layer disposed on the substrate, a first conductive pattern with a plurality of first meshes disposed on the substrate, a second conductive pattern with a plurality of second meshes disposed on the substrate and separated from the first conductive pattern, and a sealant dispensing area overlapped with the first conductive pattern and the second conductive pattern. A distance between two adjacent meshes of the first meshes is different from a distance between two adjacent meshes of the second meshes.

Abstract: A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the substrate; disposing a first doped oxide layer including a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant; disposing a mask over the first fin and removing the first doped oxide layer from the second fin; removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first doped oxide layer covering the first fin and directly onto the second fin, the second doped oxide layer including an n-type dopant or a p-type dopant that is different than the first dopant; and annealing to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin.

Abstract: Top-side cooling of Radio Frequency (RF) products in air cavity packages is provided. According to one aspect, an air cavity package comprises a substrate, a RF component mounted to the substrate, and a lid structure comprising a first material and being mounted to the substrate that covers the RF component such that a cavity is formed within the lid structure and about the RF component. At least one opening is provided in a top portion of the lid. The air cavity package also comprises a heat transfer structure comprising a second material and comprising a heat path extending from the top surface of the substrate through the opening(s) in the lid to the top outer surface of the air cavity package to provide a top-side thermal interface. In one embodiment, the lid is comprised of a molded material that absorbs RF signals and the heat transfer structure is metal.

Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.