Abstract: The present invention provides a method for forming a siliceous film. According to the method, a siliceous film having a hydrophilic surface can be formed from a polysilazane compound at a low temperature. In the method, a composition containing a polysilazane compound and a silica-conversion reaction accelerator is applied on a substrate surface to form a polysilazane film, and then a polysilazane film-treatment solution is applied thereon so that the polysilazane compound can be converted into a siliceous film at 300° C. or less. The polysilazane film-treatment solution contains a solvent, hydrogen peroxide and an alcohol.

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer.

Abstract: Decrease of the output voltage of the logic circuit is inhibited by raising the gate voltage using a capacitor. In a first transistor, a drain and a gate are electrically connected to a first wiring, and a source is electrically connected to a first node. In a second transistor, a drain is electrically connected to the first node, a source is electrically connected to a second wiring, and a gate is electrically connected to a second node. In a third transistor, a drain is electrically connected to a third wiring, and a source is electrically connected to a third node, and a gate is electrically connected to the first node. In a fourth transistor, a drain is electrically connected to the third node, a source is electrically connected to a fourth wiring, and a gate is electrically connected to the second node. In a capacitor, one electrode is electrically connected to the first node, and the other electrode is electrically connected to the third node. OS transistors are preferably used as the transistors above.

Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are stacked on a substrate. The semiconductor layer has one end connected to the substrate, has as its longer direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. Assuming at least one control gate electrode positioned in a lowermost layer of the plurality of control gate electrodes to be a first control gate electrode, the first control gate electrode comprises: a first portion; a second portion adjacent to the first portion; and a third portion connected to the first portion and the second portion.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer having a main surface, the main surface of the silicon carbide semiconductor layer being provided with a trench having a closed shape when seen in plan view, the trench including a bottom, a plurality of sidewalls continuous with the bottom, and a sidewall-connecting corner portion at a connection portion between two adjacent sidewalls of the plurality of sidewalls, the silicon carbide semiconductor device further including a gate insulating film covering the bottom and the sidewalls of the trench, and a gate electrode provided on the gate insulating film, between the bottom and an upper end of the trench, the thickness of the gate insulating film at the sidewall-connecting corner portion of the trench being greater than the thickness of the gate insulating film at a portion other than the sidewall-connecting corner portion.

Abstract: On-chip, three-dimensional MIM capacitors are provided. In one aspect, a method for forming a device includes: forming at least one MOSFET structure and at least one MIM capacitor structure on a substrate each structure including: a metal gate, and source and drain regions on opposite sides of the metal gate, and wherein the structures are buried in a dielectric; forming metal contacts in the dielectric down to the source and drain regions; forming a mask that selectively covers the MOSFET structure; removing the dielectric from uncovered portions of the MIM capacitor structure forming gaps between the metal contacts and the metal gate in the MIM capacitor structure; depositing a capacitor dielectric in the gaps; and depositing a fill metal onto the capacitor dielectric filling the gaps. A MIM capacitor and a device including an MIM capacitor are also provided.

Abstract: A method of fabricating an integrated circuit includes forming a plurality of polysilicon gate electrode structures over a plurality of fin-shaped channel structures. A portion of the plurality of polysilicon gate electrode structures may then be removed to expose a surface region of a fin-shaped channel structure in the plurality of fin-shaped channel structures. The remaining portion of the polysilicon gate electrode structures may form a plurality of polysilicon transistors. A layer of high-k dielectric material is deposited on the exposed surface region of the fin-shaped channel structure. A metal layer may be deposited over the high-k dielectric material to form at least one high-k metal gate transistor over the fin-shaped channel structure.

Abstract: A method for manufacturing a film support beam includes: providing a substrate having opposed first and second surfaces; coating a sacrificial layer on the first surface of the substrate, and patterning the sacrificial layer; depositing a dielectric film on the sacrificial layer to form a dielectric film layer, and depositing a metal film on the dielectric film layer to form a metal film layer; patterning the metal film layer, and dividing a patterned area of the metal film layer into a metal film pattern of a support beam portion and a metal film pattern of a non-support beam portion, wherein a width of the metal film pattern of the support beam portion is greater than a width of a final support beam pattern, and a width of the metal film pattern of the non-support beam portion is equal to a width of a width of a final non-support beam pattern at the moment; photoetching and etching on the metal film layer and the dielectric film layer to obtain the final support beam pattern, the final non-support beam patt

Abstract: A method of forming a fine pattern comprises depositing a modifying layer on a substrate. A photoresist layer is deposited on the modifying layer, the photoresist layer having a first pattern. The modifying layer is etched according to the first pattern of the photoresist layer. A treatment is performed to the etched modifying layer to form a second pattern, the second pattern having a smaller line width roughness (LWR) and/or line edge roughness (LER) than the first pattern. The second pattern is then etched into the substrate.

Abstract: Provided is a method for growing carbon nanotubes that enables the growth of high-density carbon nanotubes. A high frequency bias voltage is applied to a loading table on which a wafer W having a catalytic metal layer is mounted to generate a bias potential on the surface of the wafer W, and oxygen plasma is used to micronize the catalytic metal layer to form catalytic metal particles. Thereafter, hydrogen plasma is used to reduce the surface of the catalytic metal particles to form activated catalytic metal particles having an activated surface. By using each activated catalytic metal particles as a nucleus, carbon nanotubes are formed.

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

Abstract: A film containing a prescribed element and carbon is formed on a substrate, by performing a cycle a prescribed number of times, the cycle including: supplying an organic-based source containing a prescribed element and a pseudo catalyst including at least one selected from the group including a halogen compound and a boron compound, into a process chamber in which the substrate is housed, and confining the organic-based source and the pseudo catalyst in the process chamber; maintaining a state in which the organic-based source and the pseudo catalyst are confined in the process chamber; and exhausting an inside of the process chamber.

Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.

Abstract: A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.

Abstract: A semiconductor package may include a first semiconductor die, external connectors, second semiconductor dies, a mold layer, an outer packaging part, and a terrace-like edge. The external connectors may be disposed over a first surface of the first semiconductor die. The second semiconductor dies may be stacked over a second surface of the first semiconductor die. The mold layer may cover sidewalls of the second semiconductor dies. The outer packaging part may have a groove in which a stack structure of the first and second semiconductor dies are accommodated. The terrace-like edge may be disposed under an edge of the mold layer to expose a sidewall of the first semiconductor die. A portion of an outer sidewall of the mold layer may be in contact with a portion of an inner surface of the outer packaging part, and the inner surface of the outer packaging part may be spaced apart from the sidewall of the first semiconductor die by the terrace-like edge.

Abstract: A light emitting diode module includes a substrate, a first soldering section, a second soldering section, a block and a light emitting diode die. The substrate has a top surface and includes a circuit structure. The block is formed on the top surface. The soldering section and the second solder section are formed on the top surface of the substrate and electrically connected with the circuit structure. The block is positioned between the first soldering section and the second solder section. A height of the block is larger than thicknesses of the first soldering section and the second soldering section. The light emitting diode die includes a first electrode and a second electrode being respectively electrically connected to the first soldering section and the second soldering section. The block is positioned between the first soldering section and the second soldering section.

Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.

Abstract: A radiation-emitting semiconductor chip having a semiconductor body including a semi-conductor layer sequence having an active region that generates radiation, a first semiconductor layer of a first conductor, and a second semiconductor layer of a second conductor different from the first conductor, and having a carrier on which the semiconductor body is arranged, wherein a pn junction is formed in the carrier, the carrier has a first contact and a second contact on a rear side facing away from the semiconductor body, and the active area and the pn junction connect to one another in antiparallel in relation to the forward-bias direction by the first contact and the second contact.

Abstract: A method for manufacturing a thin-film transistor includes: forming a first metal layer of a pattern including a gate on a substrate through pattern formation operations; forming a gate insulation layer on the substrate and the first metal layer and forming an oxide semiconductor layer, of which an orthogonal projection is cast on the gate, on the gate insulation layer within a thin-film transistor area and an etch stop layer on the oxide semiconductor layer, in which two etching operations are applied to the patternized oxide semiconductor layer and etch stop layer; forming a patternized second metal layer on the thin-film transistor area and an exposed portion of the gate insulation layer, forming a patternized insulation protection layer on the substrate and the patternized second metal layer, and forming a patternized pixel electrode on the insulation protection layer.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a film containing a predetermined element and carbon on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a first process gas containing the predetermined element and a halogen element to the substrate; supplying a second process gas containing carbon and nitrogen to the substrate; supplying a third process gas containing carbon to the substrate; and supplying a fourth process gas to the substrate, the fourth process gas being different from each of the first to the third process gases.