Patents Examined by Abul Kalam
  • Patent number: 11417649
    Abstract: A semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer being a portion of an interconnection layer for routing, and an insulating layer extending over the substrate and configured to insulate the active region from the patterned conductive layer. The patterned conductive layer and the insulating layer serve as a gate of the transistor.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Sheng Chen, Kong-Beng Thei, Fu-Jier Fan, Jung-Hui Kao, Yi-Huan Chen, Kau-Chu Lin
  • Patent number: 11417837
    Abstract: A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: August 16, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel C. Worledge
  • Patent number: 11411098
    Abstract: A device includes a substrate and a gate structure over the substrate. The device further includes source/drain (S/D) features in the substrate. At least one of the S/D features is located in a trench. The at least one S/D feature includes a first semiconductor material covering an entirety of a bottom surface of the trench. The at least one S/D feature further includes a second semiconductor material over the first semiconductor material. The at least one S/D feature further includes a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions directly contacting the substrate. The second semiconductor material surrounds the third semiconductor material.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin
  • Patent number: 11398418
    Abstract: A semiconductor module may include: a first semiconductor chip including a first semiconductor substrate including a field effect transistor and constituted of SiC, a drain electrode and a source electrode provided on the first semiconductor substrate; a second semiconductor chip including a second semiconductor substrate including a diode, a cathode electrode and an anode electrode provided on the second semiconductor substrate; a first lead frame including a first main terminal and connected to the drain electrode and the cathode electrode; and a second lead frame including a second main terminal and connected to the source electrode and the anode electrode. A first current path extending from the second to first main terminal via the first semiconductor chip may be longer than a second current path extending from the second to first main terminal via the second semiconductor chip.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: July 26, 2022
    Assignee: DENSO CORPORATION
    Inventor: Hidekazu Sugiura
  • Patent number: 11393738
    Abstract: A bonded body of the present invention includes a ceramic member formed of ceramics and a Cu member formed of Cu or a Cu alloy. In a bonding layer formed between the ceramic member and the Cu member, an area ratio of a Cu3P phase in a region extending by up to 50 ?m toward the Cu member side from a bonding surface of the ceramic member is equal to or lower than 15%.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: July 19, 2022
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Nobuyuki Terasaki, Yoshiyuki Nagatomo
  • Patent number: 11367833
    Abstract: A memory cell can include a top lamina layer, a bottom lamina layer, and a phase change material (PCM) layer between the top lamina layer and the bottom lamina layer. The PCM layer can have a top surface in direct contact with the top lamina layer and a bottom surface in direct contact with the bottom lamina layer. The top surface of the PCM layer and the bottom surface of the PCM layer can have a structurally stabilizing width ratio.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Pavan Kumar Reddy Aella, Kolya Yastrebenetsky, Masuji Honjo
  • Patent number: 11322446
    Abstract: A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, and a bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor chip is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion is electrically connected to the first RDL pattern through the bridge die.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Jong Hoon Kim, Ki Jun Sung, Ki Bum Kim
  • Patent number: 11322524
    Abstract: A display panel is disclosed, which includes: a substrate including a display region and a border region adjacent to the display region; a first transistor disposed on the border region and including an active layer and a first conducting electrode on the substrate, wherein the first conducting electrode electrically connects to the active layer, and the first conducting electrode extends along a first direction; and a conductive layer disposed on the border region and including an opening, wherein the conductive layer partially overlaps the first conducting electrode in a top view of the border region, wherein a minimum distance from an edge of the opening to the active layer along the first direction is different from a minimum distance from another edge of the opening to the active layer along a second direction, and the first direction is different from the second direction.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: May 3, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Ling Yu, Chun-Liang Lin
  • Patent number: 11309488
    Abstract: A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 19, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel C. Worledge
  • Patent number: 11309355
    Abstract: The present disclosure provides a display device including a cathode electrode, a first anode electrode, a second anode electrode, a first light emitting layer, a first light conversion layer, a second light emitting layer, a second light conversion layer and an auxiliary electrode. The first light emitting layer is disposed between the cathode electrode and the first anode electrode. The first light conversion layer is disposed above the first light emitting layer. The second light emitting layer is disposed between the cathode electrode and the second anode electrode. The second light conversion layer is disposed above the second light emitting layer. The auxiliary electrode is electrically connected to the cathode electrode, and a portion of the auxiliary electrode is between the first light conversion layer and the second light conversion layer in a top view direction of the display device.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: April 19, 2022
    Assignee: InnoLux Corporation
    Inventors: Hsiao-Lang Lin, Tsung-Han Tsai
  • Patent number: 11289518
    Abstract: An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: March 29, 2022
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin
  • Patent number: 11276760
    Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Gopinath Bhimarasetti, Walid M. Hafez, Joodong Park, Weimin Han, Raymond E. Cotner, Chia-Hong Jan
  • Patent number: 11271128
    Abstract: An optoelectronic semiconductor device is disclosed. The device comprises a plurality of stacked p-n junctions (e.g., multi junction device). The optoelectronic semiconductor device includes a n-doped layer disposed below the p-doped layer to form a p-n layer such that electric energy is created when photons are absorbed by the p-n layer. Recesses are formed on top of the p-doped layer at the top of the plurality of stacked p-n junctions. The junctions create an offset and an interface layer is formed on top of the p-doped layer at the top of the plurality stacked p-n junctions. The device also includes a window layer disposed below the plurality stacked p-n junctions. In another aspect, one or more optical filters are inserted into a device to enhance its efficiency through photon recycling. The device can be fabricated by epitaxial growth on a substrate and removed from the substrate through a lift off process.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: March 8, 2022
    Assignee: UTICA LEASECO, LLC
    Inventors: Brendan M. Kayes, Gang He, Sylvia Spruytte, I-Kang Ding, Gregg Higashi
  • Patent number: 11271133
    Abstract: A multi-junction optoelectronic device and method of manufacture are disclosed. The method comprises providing a first p-n structure on a substrate, wherein the first p-n structure comprises a first base layer of a first semiconductor with a first bandgap such that a lattice constant of the first semiconductor matches a lattice constant of the substrate, and wherein the first semiconductor comprises a Group III-V semiconductor. The method includes providing a second p-n structure, wherein the second p-n structure comprises a second base layer of a second semiconductor with a second bandgap, wherein a lattice constant of the second semiconductor matches a lattice constant of the first semiconductor, and wherein the second semiconductor comprises a Group IV semiconductor. The method also includes lifting off the substrate the multi-junction optoelectronic device having the first p-n structure and the second p-n structure, wherein the multi-junction optoelectronic device is a flexible device.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: March 8, 2022
    Assignee: UTICA LEASECO, LLC
    Inventors: Brendan M. Kayes, Gang He
  • Patent number: 11251095
    Abstract: An analog high gain transistor is disclosed. The formation of the analog high gain transistor is highly compatible with existing CMOS processes. The analog high gain transistor includes a double well, which includes the well implants of the low voltage (LV) and intermediate voltage (IV) transistors. In addition, the analog high gain transistor includes light doped extension regions of IV transistor and a thin gate dielectric of the LV transistor.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: February 15, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Yuan Sun, Shyue Seng Jason Tan
  • Patent number: 11249363
    Abstract: According to one embodiment, a display device includes a first line which is arranged across a display portion, and includes a first end portion and a second end portion located at a non-display portion such that the display portion is located between the first and second end portions, a first switch electrically connected to the first end portion, a second switch electrically connected to the second end portion, a first terminal electrically connected to the first end portion via the first switch, and a second terminal electrically connected to the second end portion via the second switch.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: February 15, 2022
    Assignee: JAPAN DISPLAY INC.
    Inventors: Takahiro Ochiai, Hiroshi Inamura, Keita Sasanuma, Kengo Shiragami
  • Patent number: 11251085
    Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie-Cheng Deng, Horng-Huei Tseng, Yi-Jen Chen
  • Patent number: 11251191
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, where each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, drain regions contacting an upper end of a respective one of the vertical semiconductor channels, first contact via structures directly contacting a first subset of the drain regions and each having a first horizontal cross-sectional area, and second contact via structures directly contacting a second subset of the drain regions and each having a second horizontal cross-sectional area that is greater than the first horizontal cross-sectional area.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: February 15, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Lishan Weng, Fumiaki Toyama, Mohan Dunga
  • Patent number: 11245100
    Abstract: The application provides an OLED device, a manufacturing method thereof, and a display device, which reduce or eliminate color cast in an image displayed by an existing OLED device due to different lifetimes of organic materials for light emitting layers emitting light of different colors in the OLED device. In the OLED device, a luminous efficiency regulator is disposed between a cathode and a light emitting layer of at least one sub-pixel, and a vibration characteristic peak of the luminous efficiency regulator falls within a wavelength range of light emitted from the corresponding light emitting layer, such that attenuation rates of lighting luminance of the light emitting layers emitting light of different colors are kept consistent with each other over time.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: February 8, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jiliang Zhang, Xin He
  • Patent number: 11233157
    Abstract: A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 25, 2022
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee