Abstract: A display apparatus includes: a substrate having a display area and a peripheral area outside the display area; a first insulating layer over both the display area and the peripheral area; a first dam over the peripheral area and spaced apart from the first insulating layer; an electrode power supply line, at least a part of the electrode power supply line being located between the first insulating layer and the first dam; a protection conductive layer over the first insulating layer, the protection conductive layer extending over the electrode power supply line and electrically connected to the electrode power supply line; a pixel electrode over the first insulating layer in the display area; an opposite electrode over the pixel electrode; and a capping layer covering the opposite electrode and extending outside the opposite electrode such that an end of the capping layer is on the first insulating layer.

Abstract: Embodiments of the present invention are directed to forming a ternary compound using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor includes a first metal and a first ligand. The second precursor includes a second metal and a second ligand. The second ligand is selected based on the first ligand to target a second metal uptake. A substrate is exposed to the first precursor during a first pulse of an ALD cycle and the substrate is exposed to the second precursor during a second pulse of the ALD cycle, the second pulse occurring after the first pulse. The substrate is exposed to a third precursor (e.g., an oxidant) during a third pulse of the ALD cycle. The ternary compound can include a ternary oxide film.

Abstract: A semiconductor device according to embodiments includes a p-type SiC region, a gate insulating film disposed on the p-type SiC region, and a gate electrode disposed on the gate insulating film and including a p-type impurity and 3C—SiC.

Abstract: Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion of the fin is lower than about 1E17/cm3. The FinFET structure further includes an insulating layer surrounding a second portion of the fin. The dopant concentration of the second portion of the fin is greater than about 8E15/cm3. The insulating layer includes a lower layer and an upper layer, and the lower layer is disposed over a substrate connecting to the fin and has a dopant concentration greater than about 1E19/cm3.

Abstract: The present disclosure provides a mask plate and fabrication method thereof. The mask plate includes a substrate, having a first surface and a second surface, and containing a plurality of openings. The mask plate also includes a mask pattern layer, formed on the first surface of the substrate and including a plurality of pattern regions and a shield region surrounding the plurality of pattern regions. Each pattern region includes at least one through hole, and each opening formed in the substrate exposes a pattern region and the at least one through hole in the pattern region. The mask plate further includes a top substrate layer, formed on the mask pattern layer. The top substrate layer contains a plurality of grooves passing through the top substrate layer, and each groove exposes a pattern region in the mask pattern layer and exposes the at least one through hole in the pattern region.

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.

Abstract: A large area active-matrix organic light-emitting diode microdisplay and method for fabricating the same is provided which includes a panel having resolution of greater than 2,000 pixels per inch and a size of 1.4 or more inches for supporting the needs of virtual reality and augmented reality application.

Abstract: A light-emitting diode display is provided. The light-emitting diode display includes a substrate, a plurality of wires, a plurality of light-emitting areas, and at least one driver IC. The plurality of wires are formed on the substrate. The plurality of light-emitting areas include a light-emitting diode area and a virtual area. The plurality of light-emitting areas are arranged in a matrix. The virtual area of the plurality of light-emitting areas corresponds to each other. The driver IC is formed on the virtual area of the plurality of the light-emitting areas or on the plurality of the light-emitting areas.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

Abstract: A system of the present disclosure has a host testing device having a first wireless transceiver and having host testing device logic configured to transmit a test command via the first wireless transceiver. Additionally, the system has a remote testing device coupled to a system component. The remote testing device has a second wireless transceiver and remote testing device logic that receives the test command from the host testing device and executes the test command on the system component.

Abstract: A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.

Abstract: A semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer being a portion of an interconnection layer for routing, and an insulating layer extending over the substrate and configured to insulate the active region from the patterned conductive layer. The patterned conductive layer and the insulating layer serve as a gate of the transistor.

Abstract: A device includes a substrate and a gate structure over the substrate. The device further includes source/drain (S/D) features in the substrate. At least one of the S/D features is located in a trench. The at least one S/D feature includes a first semiconductor material covering an entirety of a bottom surface of the trench. The at least one S/D feature further includes a second semiconductor material over the first semiconductor material. The at least one S/D feature further includes a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions directly contacting the substrate. The second semiconductor material surrounds the third semiconductor material.

Abstract: A semiconductor module may include: a first semiconductor chip including a first semiconductor substrate including a field effect transistor and constituted of SiC, a drain electrode and a source electrode provided on the first semiconductor substrate; a second semiconductor chip including a second semiconductor substrate including a diode, a cathode electrode and an anode electrode provided on the second semiconductor substrate; a first lead frame including a first main terminal and connected to the drain electrode and the cathode electrode; and a second lead frame including a second main terminal and connected to the source electrode and the anode electrode. A first current path extending from the second to first main terminal via the first semiconductor chip may be longer than a second current path extending from the second to first main terminal via the second semiconductor chip.

Abstract: A bonded body of the present invention includes a ceramic member formed of ceramics and a Cu member formed of Cu or a Cu alloy. In a bonding layer formed between the ceramic member and the Cu member, an area ratio of a Cu3P phase in a region extending by up to 50 ?m toward the Cu member side from a bonding surface of the ceramic member is equal to or lower than 15%.

Abstract: A memory cell can include a top lamina layer, a bottom lamina layer, and a phase change material (PCM) layer between the top lamina layer and the bottom lamina layer. The PCM layer can have a top surface in direct contact with the top lamina layer and a bottom surface in direct contact with the bottom lamina layer. The top surface of the PCM layer and the bottom surface of the PCM layer can have a structurally stabilizing width ratio.

Abstract: A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, and a bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor chip is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion is electrically connected to the first RDL pattern through the bridge die.

Abstract: A display panel is disclosed, which includes: a substrate including a display region and a border region adjacent to the display region; a first transistor disposed on the border region and including an active layer and a first conducting electrode on the substrate, wherein the first conducting electrode electrically connects to the active layer, and the first conducting electrode extends along a first direction; and a conductive layer disposed on the border region and including an opening, wherein the conductive layer partially overlaps the first conducting electrode in a top view of the border region, wherein a minimum distance from an edge of the opening to the active layer along the first direction is different from a minimum distance from another edge of the opening to the active layer along a second direction, and the first direction is different from the second direction.

Abstract: The present disclosure provides a display device including a cathode electrode, a first anode electrode, a second anode electrode, a first light emitting layer, a first light conversion layer, a second light emitting layer, a second light conversion layer and an auxiliary electrode. The first light emitting layer is disposed between the cathode electrode and the first anode electrode. The first light conversion layer is disposed above the first light emitting layer. The second light emitting layer is disposed between the cathode electrode and the second anode electrode. The second light conversion layer is disposed above the second light emitting layer. The auxiliary electrode is electrically connected to the cathode electrode, and a portion of the auxiliary electrode is between the first light conversion layer and the second light conversion layer in a top view direction of the display device.

Abstract: A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.