Patents Examined by Abul Kalam
  • Patent number: 10847551
    Abstract: A thin film transistor substrate includes a substrate; a first thin film transistor on the substrate and including a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor on the substrate and including a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode; an intermediate insulating layer on the first gate electrode and the second gate electrode and under the oxide semiconductor layer; and a dummy layer between the first source electrode and the intermediate insulating layer and between the first drain electrode and the intermediate insulating layer, wherein the dummy layer is formed of a same material as the oxide semiconductor layer.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: November 24, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Hyunsoo Shin, Uijin Chung
  • Patent number: 10847534
    Abstract: Embodiments of staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed above the substrate and including conductor/dielectric layer pairs stacked alternatingly, and an array of memory strings each extending vertically through an inner region of the memory stack. An outer region of the memory stack includes a first staircase structure disposed on the substrate and a second staircase structure disposed above the first staircase structure. First edges of the conductor/dielectric layer pairs in the first staircase structure along a vertical direction away from the substrate are staggered laterally away from the array of memory strings. Second edges of the conductor/dielectric layer pairs in the second staircase structure along the vertical direction away from the substrate are staggered laterally toward the array of memory strings.
    Type: Grant
    Filed: September 22, 2018
    Date of Patent: November 24, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Shao-Fu Sanford Chu
  • Patent number: 10847686
    Abstract: A method of producing optoelectronic components includes providing a carrier; arranging optoelectronic semiconductor chips on the carrier; forming a conversion layer for radiation conversion on the carrier, wherein the optoelectronic semiconductor chips are surrounded by the conversion layer; and carrying out a singulation process to form separate optoelectronic components, wherein at least the conversion layer is severed.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: November 24, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Martin Brandl, Tobias Gebuhr, Thomas Schwarz
  • Patent number: 10842016
    Abstract: A compact and efficient LED array lighting component comprising a circuit board with an array of LED chips mounted on it and electrically interconnected. A plurality of primary lenses is included, each of which is formed directly over each LED chip and/or a sub-group of the LED chips. A heat sink is included with the circuit board mounted to the heat sink so that heat from the LED chips spreads into the heat sink. In some embodiments the circuit board can be thermally conductive and electrically insulating. Method of forming an LED component are also disclosed utilizing chip-on-board mounting techniques for mounting the LED chips on the circuit board, and molding of the primary lenses directly over the LED chips individually or in sub-groups of LED chips.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: November 17, 2020
    Assignee: Cree, Inc.
    Inventors: Chandan Bhat, Theodore Douglas Lowes, Julio Garceran, Bernd Keller
  • Patent number: 10840354
    Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Thamarai S. Devarajan, Balasubramanian Pranatharthiharan, Sanjay C. Mehta, Muthumanickam Sankarapandian
  • Patent number: 10833094
    Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: November 10, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
  • Patent number: 10770360
    Abstract: A method for fabricating a semiconductor structure includes providing a base structure including a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in a first transistor region, and a plurality of second openings formed in the dielectric layer in a second transistor region. The method also includes forming a first work function layer an the dielectric layer covering bottom and sidewall surfaces of the first and the second openings, forming a first sacrificial layer in each first opening and each second opening with a top surface lower than the top surface of the dielectric layer, removing a portion of the first work function layer exposed by the first sacrificial layer, removing the first work function layer formed in each first opening, and forming a second work function layer and a gate electrode in each first opening and each second opening.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 8, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10748787
    Abstract: A semiconductor device includes an insulating carrier structure comprised of an insulating inorganic material. The carrier structure has a receptacle in which a semiconductor chip is disposed. The semiconductor chip has a first side, a second side and a lateral rim. The carrier structure laterally surrounds the semiconductor chip and the lateral rim. The semiconductor device also includes a metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Carsten von Koblinski, Ulrike Fastner, Andre Brockmeier, Peter Zorn
  • Patent number: 10727370
    Abstract: Provided is an optical device including an active layer, which includes two outer barriers and a coupled quantum well between the two outer barriers. The coupled quantum well includes a first quantum well layer, a second quantum well layer, a third quantum well layer, a first coupling barrier between the first quantum well layer and the second quantum well layer, and a second coupling barrier between the second quantum well layer and the third quantum well layer. The second quantum well layer is between the first quantum well layer and the third quantum well layer. An energy band gap of the second quantum well layer is less than an energy band gap of the first quantum well layer, and an energy band gap of the third quantum well layer is equal to or less than the energy band gap of the second quantum well layer.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byunghoon Na, Changyoung Park, Yonghwa Park
  • Patent number: 10714531
    Abstract: Focal plane arrays and infrared detector device having a transparent common ground structure and methods of their fabrication are disclosed. In one embodiment, a front-side illuminated infrared detector device includes a contact layer and a detector structure adjacent to the contact layer. The detector structure is capable of absorbing radiation. The front-side illuminated infrared detector device further includes a common ground structure adjacent the detector structure, wherein the common ground structure is transmissive to radiation having a wavelength in a predetermined spectral band, and the common ground structure has a bandgap that is wider than a bandgap of the detector structure. The front-side illuminated infrared detector device further includes an optical layer adjacent the common ground structure.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: July 14, 2020
    Assignee: L3 Cincinnati Electronics Corporation
    Inventors: Yajun Wei, Steven Allen, Michael Garter, Mark Greiner, David Forrai, Darrel Endres
  • Patent number: 10707314
    Abstract: A stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer is formed over a substrate. A two-dimensional array of openings is formed through the dielectric matrix layer and the one-dimensional array of gate electrode strips. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of openings. Each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips. Gate dielectrics are formed on inner sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surrounding gate electrodes is formed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 7, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Seje Takaki, Jongsun Sel, Hisakazu Otoi, Chao Feng Yeh
  • Patent number: 10685889
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate including a core region and a peripheral region, forming a plurality of first fin structures in the peripheral region and a plurality of second fin structures in the core region, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure, and forming a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure and then forming a first gate oxide layer on the exposed portion of each first fin structure, and removing each second dummy gate structure. Finally, the method includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10684499
    Abstract: A splicing screen includes: at least two display panels spliced together, each display panel having a display surface; a curved area bending towards a back side of the display surface at a splicing area; and a substantially flat area; a transparent cover disposed at a side of the display surface and covering at least the curved area of each display panel; and a plurality of support portions between the transparent cover and the curved area of each of the display panels and forming a plurality of meshes extending from the display panel to the transparent cover, an inner wall of each mesh having a reflective surface.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 16, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Mingchao Wang, Junwei Wang, Dongxi Li
  • Patent number: 10665724
    Abstract: A method and apparatus wherein the method comprises: providing at least one electrode within a semiconductor layer wherein the semiconductor layer is provided on a first side of a wafer; thinning the wafer to produce a thinned wafer; providing graphene on a second side of the thinned wafer; attaching the semiconductor layer to an electrical interface on the first side of the thinned wafer; and providing at least one electrical connection from the graphene to the electrical interface so as to form a transistor comprising the at least one electrode and the graphene.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 26, 2020
    Assignee: LytEn, Inc.
    Inventors: Katri Pohjonen, Sami Kallioinen, Markku Rouvala
  • Patent number: 10658403
    Abstract: A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: May 19, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuanfu Liu
  • Patent number: 10651429
    Abstract: An organic light-emitting diode (OLED) illuminating lamp sheet and a manufacturing method thereof are provided. The method for manufacturing an OLED illuminating lamp sheet includes: manufacturing an array substrate, the array substrate includes a first base and a first electrode formed on the first base; bonding an electrostatic film to a surface of the array substrate provided with the first electrode, forming a patterned electrostatic film by patterning the electrostatic film, and forming an organic film layer by taking the patterned electrostatic film as a mask; forming a second electrode and obtaining an OLED element; and encapsulating the OLED element and obtaining an OLED illuminating lamp sheet.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: May 12, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jie Sun, Chung Chun Lee, Chieh Hsing Chung
  • Patent number: 10643862
    Abstract: The present invention discloses a system-level packaging method and packaging system based on 3D printing.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 5, 2020
    Assignee: INSTITUTE OF GEOLOGY AND GEOPHYSICS CHINESE ACADEMY OF SCIENCES
    Inventors: Zongwei Li, Xingyin Xiong, Kedu Han, Changchun Yang
  • Patent number: 10643915
    Abstract: A lead bonding structure includes: a plurality of leads extending outward from a package; and a plurality of electrode pads formed on a circuit board. The plurality of leads are soldered to the electrode pads, respectively. Each of the leads includes a lower wide portion having a width dimension greater than a width dimension of each of the electrode pads. The lower wide portion of each of the leads is soldered to the corresponding electrode pad.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: May 5, 2020
    Assignee: Japan Aviation Electronics Industry, Ltd.
    Inventors: Hiroshi Akimoto, Takushi Yoshida
  • Patent number: 10644032
    Abstract: The present invention discloses a flexible display substrate including a first flexible substrate and a plurality of display elements disposed on a first side of the first flexible substrate, each of the display elements including a thin film transistor. The flexible display substrate further includes a plurality of protrusions each provided on a second side of the first flexible substrate opposite to the first side and corresponding to a respective thin film transistor in a thickness direction of the first flexible substrate. A projection area of each protrusion, in the thickness direction of the first flexible substrate, on the second side of the first flexible substrate at least partially overlaps with a projection area of the thin film transistor corresponding to the protrusion, in the thickness direction of the first flexible substrate, on the second side of the first flexible substrate.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: May 5, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongfei Cheng, Yuxin Zhang
  • Patent number: 10629702
    Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Thamarai S. Devarajan, Balasubramanian Pranatharthiharan, Sanjay C. Mehta, Muthumanickam Sankarapandian