Abstract: A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

Abstract: A semiconductor power device includes a substrate, a buffer structure formed on the substrate, a barrier structure formed on the buffer structure, a channel layer formed on the barrier structure, and a barrier layer formed on the channel layer. The barrier structure includes a first functional layer on the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer. A material of the first back-barrier layer comprises Alx1Ga1-x1N, a material of the first functional layer comprises Alx2Ga1-x2N, 0<x1?1, 0?x2?1, and x1?x2. The interlayer includes a carbon doped or an iron doped material.

Abstract: A display apparatus includes: a substrate on which a first area, a second area spaced apart from the first area, and a bending area between a first area and a second area and bent along a bending axis are defined; a first thin-film transistor (“TFT”) and a second TFT; and a first conductive layer and a second conductive layer. The first TFT includes: a first active layer including polycrystalline silicon; a first gate electrode; and a first electrode disposed at a level which is the same as a level of the first conductive layer, and the second TFT includes: a second active layer including an oxide semiconductor; a second gate electrode; and a second electrode disposed at a level which is the same as a level of the second conductive layer.

Abstract: A fabrication method for a static random-access memory device is provided. The method includes: forming an initial substrate including at least one first region; and removing a portion of the initial substrate in the first region, to forming a substrate, first fins on the substrate, and second initial fins on the substrate. A width of the second initial fins is different from a width of the first fins. A portion of the first fins is used to form pass-gate transistors, and another portion of the first fins and the second initial fins are used to form pull-down transistors.

Abstract: A chip-on-film package including a flexible substrate, first test pads, second test pads, first connecting wires, second connecting wires and a chip is provided. The flexible substrate includes at least one segment. Each segment has a central portion and a first side portion and a second side portion located at two opposite sides of the central portion. The chip disposed on the central portion includes first connecting pads and second connecting pads. The first test pads and the second test pads are disposed on the first side portion. Two ends of each of the first connecting wires are connected to the corresponding first connecting pad and the corresponding first test pad. Two ends of each of the second connecting wires are connected to the corresponding second connecting pad and the corresponding second test pad. Each of the second connecting wires includes a first section located at the second side portion.

Abstract: A display device includes a display panel displaying an image to a front surface and a first impact resistance layer disposed on the front surface of the display panel, wherein the first impact resistance layer includes a matrix layer including an internal space and a gel particle filled in the space.

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

Abstract: Disclosed is an apparatus and method for classifying a motion state of a mobile device comprising: determining a first motion state associated with a highest probability value and with a first confidence level greater than a first threshold; entering the first motion state; while the first motion state is active, determining a second motion state associated with a highest probability value and with a second confidence level greater than the first threshold, the second motion state being different from the first motion state; determining whether the second motion state is to be entered; and in response to determining that the second motion state is to be entered, entering the second motion state.

Abstract: A flexible display device is discussed. The flexible display device includes a substrate having multiple signal lines arranged on the substrate; a transistor disposed on the substrate, the transistor including a gate electrode, a source electrode, and a drain electrode; and a second electrode disposed to correspond to a first electrode connected to the source electrode or the drain electrode of the transistor, wherein at least one of the multiple signal lines, the gate electrode, the source electrode, the drain electrode, and the second electrode is formed of a conductor having a metal nanowire structure and a polymer substance, the metal nonwire structure being disposed in the polymer substance. Also discussed is a method of manufacturing the flexible display device.

Abstract: The present disclosure provides a display substrate and a manufacturing method thereof, and a display apparatus, the manufacturing method comprises: forming a base; forming a thin film transistor on the base, the thin film transistor comprises a gate, a source, a drain and an active layer, a first insulating layer is formed on the base, and a second insulating layer is formed between the gate and the active layer, the active layer is formed in the first insulating layer; forming a third insulating layer above the thin film transistor; forming a pixel electrode above the third insulating layer; forming a fourth insulating layer above the pixel electrode, a material of at least one of the base, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer includes an organic material, and a material of at least one of them includes an inorganic material.

Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.

Abstract: The present disclosure provides a CMOS transistor and a method for fabricating the same, a display panel and a display device. The method includes: forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate; and injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process, wherein a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer.

Abstract: The present invention provides a display substrate and a manufacturing method thereof, and a display device. The display substrate comprises a base substrate, and gate lines, data lines, a gate driving circuit and a source driving circuit on the base substrate, the gate lines and the data lines define pixel units, the pixel unit comprises a thin film transistor and a pixel electrode, the data lines are connected to the source driving circuit, the display substrate further comprising gate line connection wires on the base substrate, the gate lines are connected to the gate driving circuit through the gate line connection wires, the gate driving circuit and the source driving circuit are located at edge positions on the base substrate in an extending direction of the data lines, and they are opposite to each other. The widths of the bezel in the extending direction of the gate lines are reduced.

Abstract: An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.

Abstract: An electronic device including a semiconductor memory is provided to include a mat region comprising a plurality of memory cells, each including a second transistor; a first switching region located at a side of the mat region and including first transistors; and a second switching region located at the other side of the mat region and including third transistors, wherein the second transistors comprise: a plurality of second active regions; and a plurality of second gate structures extending in the first direction to cross the second active regions, wherein each second active regions is divided into a first side portion, a middle portion and a second side portion that are arranged alternately and repeatedly in the first direction, wherein the first transistors and the third transistors include their active regions and gate structures which are arranged in the same manner as those of the second transistors.

Abstract: A semiconductor heterostructure for an optoelectronic device includes a base semiconductor layer having one or more semiconductor heterostructure mesas located thereon. One or more of the mesas can include a set of active regions having multiple main peaks of radiative recombination at differing wavelengths. For example, a mesa can include two or more active regions, each of which has a different wavelength for the corresponding main peak of radiative recombination. The active regions can be configured to be operated simultaneously or can be capable of independent operation. A system can include one or more optoelectronic devices, each of which can be operated as an emitter or a detector.

Abstract: According to a flexible OLED device production method of the present disclosure, a multilayer stack (100) is provided which includes a glass base (10), a functional layer region (20) including a TFT layer (20A) and an OLED layer (20B), and a synthetic resin film (30) provided between the glass base (10) and the functional layer region (20) and bound to the glass base (10). In a dry gas atmosphere whose dew point is not more than ?50° C., the multilayer stack (100) is separated into a first portion (110) and a second portion (120), and a surface (30s) of the synthetic resin film (30) is exposed to the dry gas atmosphere, the first portion (110) including the functional layer region (20) and the synthetic resin film (30), the second portion (120) including the glass base (10). The first portion (110) is transported from the dry gas atmosphere to a reduced-pressure atmosphere R, and a protection layer (60) is formed on the surface (30s) of the synthetic resin film (30) in the reduced-pressure atmosphere R.

Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

Abstract: A semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer being a portion of an interconnection layer for routing, and an insulating layer extending over the substrate and configured to insulate the active region from the patterned conductive layer. The patterned conductive layer and the insulating layer serve as a gate of the transistor.