Patents Examined by Adam M Queler
  • Patent number: 11099758
    Abstract: In one embodiment, a method includes allocating, by an operating system of a computing device, computer-implemented memory into a discardable portion and a durable portion; receiving, from a computer-executable program, a designation indicator of a particular data file that is associated with the computer-executable program indicating that the particular file is to be stored in the discardable portion of the memory and in response, storing the particular data file in one or more particular pages of the discardable portion of the memory; identifying an occurrence of a computing condition and in response, marking the one or more particular pages that include the particular data file as invalid for the computer-executable program; receiving, from the computer-executable program, a request for the particular data file; and in response to receiving the request, providing, to the computer-executable program, a notification that the particular data file is invalid for the computer-executable program.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: August 24, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Bernhard Poess, Vadim Victor Spivak, Christoph Klee
  • Patent number: 11093397
    Abstract: Use of a survival queue to manage a container-based flash cache is disclosed. In various embodiments, a corresponding survival time is associated with each of a plurality of containers stored in a flash cache, each container comprising a plurality of data blocks. The survival time may be determined based at least in part on a calculated proportion of relatively recently accessed data blocks associated with the container is associated with the container. A container to evict from the flash cache is selected based at least in part on a determination that the corresponding survival time of the selected container has expired.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 17, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Frederick Douglis, Cheng Li, Philip Shilane, Grant Wallace
  • Patent number: 11086898
    Abstract: Methods and apparatus for token-based admission control for replicated writes are disclosed. Data objects are divided into partitions, and corresponding to each partition, at least a master replica and a slave replica are stored. A determination as to whether to accept a write request directed to the partition is made based at least in part on one or more of (a) available throughput capacity at the master replica, and (b) an indication, obtained using a token-based protocol, of available throughput capacity at the slave replica. If the write request is accepted, one or more data modification operations are initiated.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 10, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Kiran-Kumar Muniswamy-Reddy, Bjorn Patrick Swift, Miguel Mascarenhas Filipe, Timothy Andrew Rath, Stefano Stefani, Yijun Lu, Wei Xiao, Stuart Henry Seelye Marshall, James R. Hamilton
  • Patent number: 11087797
    Abstract: There is provided a tape recording apparatus system capable of improving writing performance and maintaining tape recording density, for a multiple data writing request accompanied by a lot of synchronization requests from a host. The system is a tape storage system including two or more tape drives each of which has a tape mounted thereon and is provided with a buffer divided in fixed-length segments, and connected to a host that sends multiple data and a synchronization request at a predetermined timing to these tape drives.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Atsushi Abe, Takashi Katagiri, Motoko Oe, Setsuko Masuda, Yutaka Oishi, Noriko Yamamoto, Katsumi Yoshimura
  • Patent number: 11055018
    Abstract: Example storage systems, storage nodes, and methods provide parallel storage node processing of data functions, such as map-reduce functions. Storage nodes are configured to decode erasure encoded symbols, identify subunits of a data unit from the decoded symbols, and process the subunits in parallel using map-functions to generate intermediate contexts. A reduce-function may be used to determine a function result using the intermediate contexts.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Stijn Devriendt, Thomas Demoor, Ewan Higgs
  • Patent number: 11010082
    Abstract: Techniques for performing space accounting for volume families. The techniques include maintaining two counters for each volume family, including a first counter that tracks a first amount of physical space allocated to volumes in the volume family based on the number of pages written to the volumes, and a second counter that tracks a second amount of physical space owned by the volume family, and maintaining a third counter for each volume in each branch of the volume family that tracks a number of pages among a total number of pages written to the volume that were overwritten in the immediate sequential next volume in the same branch as the volume. By maintaining, for each volume family, the first counter and the second counter, and, for each volume in the volume family, the third counter, space accounting metrics can be obtained that allow data storage activities to be performed efficiently.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 18, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Kumari Bijayalaxmi Nanda, Michal Marko, Soumyadeep Sen, Alexander S. Mathews
  • Patent number: 11010053
    Abstract: The present application is directed to a memory-access-multiplexing memory controller that can multiplex memory accesses from multiple hardware threads, cores, and processors according to externally specified policies or parameters, including policies or parameters set by management layers within a virtualized computer system. A memory-access-multiplexing memory controller provides, at the physical-hardware level, a basis for ensuring rational and policy-driven sharing of the memory-access resource among multiple hardware threads, cores, and/or processors.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: May 18, 2021
    Assignee: VMware, Inc.
    Inventor: Bhavesh Mehta
  • Patent number: 10977215
    Abstract: A data de-duplication system includes a storage device that includes multiple data sets, a fixed read-only storage area, and a processing device configured to perform certain functions. The system determines whether each of the multiple data sets has met a common pattern criteria, and if so, identifies the data set as a candidate data set for de-duplication. The common pattern criteria is indicative of whether a chunk data is frequently accessed among multiple users on a cloud. The system stores data in at least one candidate data sets in the fixed storage area. For each of the at least candidate data sets, the system generates a unique pointer that corresponds to a location of the at least one candidate data sets in the fixed storage area. The system further uses the pointers to de-duplicate the at least one candidate data sets.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ezra Hartz, Heiko Schloesser
  • Patent number: 10956342
    Abstract: A multi-controller memory system includes a flexible channel memory controller coupled to at least first and second physical interfaces. The second physical interface is also coupled to an auxiliary memory controller. The physical interfaces may be coupled to separate memory modules. In a single-channel control mode, the memory controllers respectively control the memory modules coupled to the first and second physical interface. In a multi-channel control mode, the flexible channel memory controller controls both memory modules while the auxiliary memory controller is inactive. In a single-channel control mode, the memory controllers coordinate restricted memory control commands which access a resource shared by both modules, by one controller transmitting a request signal for the resource to the other controller, awaiting an acknowledgment signal from the other controller, and maintaining transmission of the request signal until the use of the resource is completed.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: March 23, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: John MacLaren, Jerome J. Johnson, Landon Laws, Anne Hughes
  • Patent number: 10936219
    Abstract: A switch-based inter-device notational data movement system includes a first processing system in a first chassis that provides a first thread, a second processing system in a second chassis that provides a second thread, each of which are coupled to a memory system by a switch device. A controller device coupled to the switch device receives a data transfer communication from the first thread requesting to transfer data to the second thread. That data stored in a first portion of the memory system associated with the first thread in a memory fabric management database included in the switch device. The controller device then modifies notational reference information in the memory fabric management database to disassociate the first portion of the memory system and the first thread and associate the first portion of the memory system with the second thread, allowing the second thread to reference the data using request/respond operation.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: March 2, 2021
    Assignee: Dell Products L.P.
    Inventors: Shyamkumar T. Iyer, William Price Dawkins
  • Patent number: 10936216
    Abstract: A method and system for storage exhaustion estimation. Specifically, the method and system disclosed herein entail deriving a timeline for the depletion of available storage capacity on a backup storage array based on the data backup dynamics of various user clients. The timeline may deduce storage capacity availability in terms of future successful backup cycles, which may serve to address critical issues involving the administration of the backup storage array.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Aaditya Rakesh Bansal, Tushar B Dethe
  • Patent number: 10824556
    Abstract: A computer-implemented method according to one embodiment includes determining resource usage of at least a first module in a grid storage system having multiple modules and approximately equal resource usage across the multiple modules of the grid storage system. The computer-implemented method further includes determining a garbage collection cost in the grid storage system by stopping garbage collection in a second of the modules of the grid storage system, determining a resource usage in the second module upon stopping the garbage collection, and comparing the resource usage in the second module to the resource usage of the at least the first module. The method further includes adjusting an amount of garbage collection based on both the garbage collection cost and the resource usage.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: November 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Asaf Porat-Stoler, Yosef Shatsky, Sergey Marenkov, Jonathan Fischer-Toubol, Afief Halumi
  • Patent number: 10776259
    Abstract: A method for data processing is disclosed. A blank state is determined for several data bits based on a majority decision. Each data bit is represented by a group of at least two memory cells. The at least two memory cells of this group are complementary cells of a differential read memory.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: September 15, 2020
    Assignee: Infineon Technologies AG
    Inventors: Jan Otterstedt, Thomas Kern
  • Patent number: 10719270
    Abstract: A data storage device include a nonvolatile memory device having a plurality of super blocks; a memory configured to store a free first logical page list including position information of free first logical pages which are present in completely used super blocks, among the plurality of super blocks; and a processor configured to select a super block having no valid page and having the free first logical pages, among the completely used super blocks, based on the free first logical page list, and to use the free first logical pages in the selected super block during a write operation.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung Jin Park, Jong Min Lee
  • Patent number: 10628314
    Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Blake, Timothy C. Bronson, Pak-kin Mak, Vesselina K. Papazova, Robert J. Sonnelitter, III
  • Patent number: 10628313
    Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Blake, Timothy C. Bronson, Pak-kin Mak, Vesselina K. Papazova, Robert J. Sonnelitter, III
  • Patent number: 10564870
    Abstract: The allocation of resources, such as for data storage, can be performed based at least in part upon predicted values for utilization and growth, among other such values. Various features can be used to predict the initial utilization and growth rate for a data volume, and these predicted values can be used to determine where to place the volumes. The features can include, for example, customer usage history, volume type, volume purpose, type of attached virtual machine, and the like. The ability to predict actual usage can enable capacity to be allocated based on an as-needed basis instead of providing large blocks of allocated capacity that would go largely unused. Similar predictions can be used to determine whether and where to migrate data volumes so as to maintain sufficient capacity across a group of resources.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: February 18, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Magee Greenwood, Gary Michael Herndon, Jr., Surya Prakash Dhoolam, Mitchell Gannon Flaherty
  • Patent number: 10564895
    Abstract: An infrastructure, method and controller card for managing flash memory in a storage infrastructure. A system is provided that includes flash memory; and a controller that includes: an I/O request handler for handling standard read and write (R/W) operations requested from a host; a garbage collection (GC) system that performs a GC process on the flash memory in response to a threshold condition, wherein the GC process includes GC-induced R/W operations; and a scheduler that interleaves standard R/W operations with GC-induced R/W operations, wherein the scheduler calculates minimum and maximum boundaries for GC-induced R/W operations for a GC process based on an estimated GC latency.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 18, 2020
    Assignee: SCALEFLUX, INC.
    Inventors: Qi Wu, Duy Nguyen, Prathamesh Amritkar, Qing Li
  • Patent number: 10558373
    Abstract: A method, system, and computer program product for providing, via a provisioning engine, a scalable set of indexed key-value pairs enabled to store objects in a data storage environment; wherein the data representing the objects is enabled to be spread across arrays in the data storage environment; wherein additional arrays are enabled to be added to the data storage environment and included in the indexed key-value pairs; wherein the data stored across the arrays may be balanced.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 11, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Shashwat Srivastav, Vishrut Shah, Sriram Sankaran, Jun Luo, Chen Wang, Huapeng Yuan, Subba Gaddamadugu, Qi Zhang, Jie Song, Andrew Robertson, Peter Musial
  • Patent number: 10545865
    Abstract: A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit may multiply bit vectors representing key values by a sparse bit matrix and may add a constant bit vector to the results. The hash function sub-circuits may be constructed using odd-parity circuits that accept as inputs subsets of the bits of the bit vectors representing the key values. The sparse bit matrices may be chosen or generated so that there are at least twice as many 0-bits per row as 1-bits or there is an upper bound on the number of 1-bits per row. Using sparse bit matrices in the hash function sub-circuits may allow the lookup circuit to perform lookup operations with very low latency.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 28, 2020
    Assignee: Oracle International Corporation
    Inventors: Guy L. Steele, Jr., David R. Chase