Patents Examined by Adam M Queler
  • Patent number: 9959936
    Abstract: The present disclosure describes apparatuses and techniques that enable temperature-based memory access. In some aspects, a request to access a memory device is received. In response to the request, respective temperatures are determined for multiple locations of the memory device. Based on these respective temperatures, a selection can be made of which of the multiple locations to access. Alternately or additionally, an order in which to access the multiple locations can be determined based on the respective temperatures. The location(s) of the memory device are then accessed based on the selection or the determined order effective to minimize an increase in the memory device's temperature.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: May 1, 2018
    Assignee: Marvell International Ltd.
    Inventor: Jong-uk Song
  • Patent number: 9940229
    Abstract: Technologies for persistent memory programming include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may assign a virtual memory address of a target location in persistent memory to a persistent memory pointer using persistent pointer strategy, and may dereference the pointer using the same strategy. Persistent pointer strategies include off-holder, ID-in-value, optimistic rectification, and pessimistic rectification. The computing device may log changes to persistent memory during the execution of a data consistency section, and commit changes to the persistent memory when the last data consistency section ends. Data consistency sections may be grouped by log group identifier. Using type metadata stored in the nonvolatile region, the computing device may identify the type of a root object within the nonvolatile region and then recursively identify the type of all objects referenced by the root object. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Xipeng Shen, Youfeng Wu, Cheng Wang, Hyunchul Park, Hongbo Rong
  • Patent number: 9933944
    Abstract: An information processing system comprises a processor. The processor executes a process that causes the information processing system to perform first writing, when requested to write data, data from which to subtract remainder data obtained by dividing a data size of write target data by a first data size of first processing unit data, the first data size being a size of processing unit data of a reading/writing process in a first storage device, in the write target data requested to be written to the first storage device and second writing the remainder data not being written by the first writing to a second storage device in which to set a second data size of second processing unit data, the second data size being smaller than the first data size of the first processing unit data.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 3, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Atsushi Nukariya, Tsuyoshi Hashimoto
  • Patent number: 9928181
    Abstract: A computing device within a reflective memory system includes a memory block and a special purpose processor. The memory block includes a plurality of memory areas, which are configured to store data of a corresponding one of a plurality of external devices. The special purpose processor is configured to intercept a write request. The write request is associated with a first external device of the plurality of external devices, and the first external device is associated with a first memory area of the plurality of memory areas. The special purpose processor is configured to determine whether the write request is valid or invalid, write the data of the first external device to the first memory area if the write request is valid, and prevent the data of the first external device from being written to the memory block if the write request is invalid.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: March 27, 2018
    Assignee: GE-HITACHI NUCLEAR ENERGY AMERICAS, LLC
    Inventors: Oscar L. Meek, Gregory S. Droba
  • Patent number: 9928157
    Abstract: A method for filtering multiple in-memory trace buffers for event ranges is provided. The method includes allocating a plurality of main trace buffers, based on the number of central processing units (CPU) participating in a trace. Each CPU has a dedicated main trace buffer, and each main trace buffer is circular. Each main trace buffer is divided into an equal number of sub-buffers. A plurality of events is written to the current sub-buffer. When the current sub-buffer is filled, events are written to the next sub-buffer. Events are extracted from at least one of the sub-buffers, starting with the sub-buffer that includes a compare time and ending at the end of the main trace buffer.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
  • Patent number: 9880928
    Abstract: Improved techniques for storing data involve storing compressed data in blocks of a first AU size and storing uncompressed data in blocks of a second AU size larger than the first AU size. For example, when a storage processor compresses a chunk of data, the storage processor checks whether the compressed chunk fits in the smaller AU size. If the compressed chunk fits, then the storage processor stores a compressed chunk in a block having the smaller AU size. Otherwise, the storage processor stores the uncompressed chunk in a block having the larger AU size. Advantageously, the improved techniques promote better disk and cache utilization, which improves performance without disrupting block mapping.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: January 30, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Jean-Pierre Bono, Philippe Armangau
  • Patent number: 9858193
    Abstract: A computer-implemented method, computer program product and computing system for defining a cache storage portion within a cache storage device coupled to a computing device. An application storage portion is defined within the cache storage device coupled to the computing device. The cache storage portion is configured to store cache data and the application storage portion is configured to store application data.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: January 2, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Roy E. Clark, Randall H. Shain, Barry Ader, Daniel S. Cobb
  • Patent number: 9857994
    Abstract: A storage controller that performs control for storing in memory areas of a storage device, data that is grouped into redundant data in blocks each having a given data size. The storage controller includes a memory unit configured to store therein group information created by grouping performed such that logical addresses for a writing destination identified from a data writing request are correlated with the blocks; and a control unit configured to count in response to a data reading request, number of times of reading from a group including logical addresses for a reading destination identified from the reading request, based on the group information, and issues any one among a reading request that includes the logical addresses for the reading destination and a reading request that includes logical addresses for a memory destination of redundant data corresponding to data of the logical addresses for the reading destination.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: January 2, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Hironori Saito
  • Patent number: 9836396
    Abstract: A last-level cache controller includes a system state monitor and a cache partitioning module. The system state monitor is configured to obtain a latency sensitivity factor, off-chip latency factors, and cache miss information for each of the processor cores. The cache partitioning module is configured to: obtain a first weighted latency according to the latency sensitivity factor, the off-chip latency factors and a first entry of the cache miss information that corresponds to a first cache partition configuration for each of the processor cores; obtain a first aggregated weighted latency according to the first weighted latency of each of the processor cores; determine whether a partition criterion is satisfied, where the partition criterion takes the first aggregated weighted latency into consideration; and partition the cache ways of the last-level cache using the first partition configuration when determining that the partition criterion is satisfied.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: December 5, 2017
    Assignees: MEDIATEK INC., NATIONAL TAIWAN UNIVERSITY
    Inventors: Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang
  • Patent number: 9811465
    Abstract: A plurality of nodes includes an I/O (Input/Output) node and a plurality of computation nodes. Each computation node sends an I/O request to the I/O node. The I/O node includes a first storage device which stores data to be written or read according to the I/O request and a first memory device on which a first cache area is based to temporarily store the data written in the first storage device or read from the first storage device. The computation node includes a second memory device on which the second cache area is based to temporarily store the data according to the I/O request. At least one of the I/O node and the computation node stores management information which contains information on a physical storage area in the cache area of the other one of the I/O node and the computation node, and information on a virtual storage area which is associated with the physical storage area and has a part of its own cache area.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: November 7, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhide Aikoh, Keisuke Hatasaki
  • Patent number: 9800523
    Abstract: A scheduling method for virtual processors based on the affinity of NUMA high-performance network buffer resources, including: in a NUMA architecture, when a network interface card (NIC) of a virtual machine is started, getting distribution of the buffer of the NIC on each NUMA node; getting affinities of each NUMA node for the buffer of the network interface card on the basis of an affinity relationship between each NUMA node; determining a target NUMA node in combination with the distribution of the buffer of the NIC on each NUMA node and NUMA node affinities for the buffer of the NIC; scheduling the virtual processor to the CPU on the target NUMA node. The problem of affinity between the VCPU of the virtual machine and the buffer of the NIC not being optimal in the NUMA architecture is solved to reduce the speed of VCPU processing network packets.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: October 24, 2017
    Assignee: Shanghai Jiao Tong University
    Inventors: Haibing Guan, Ruhui Ma, Jian Li, Xiaolong Jia
  • Patent number: 9798475
    Abstract: According to one embodiment, a controller writes data stored in a first data group of a plurality of data groups into a first block group of the plurality of block groups and writes data stored in a second data group of the plurality of data groups into a second block group of the plurality of block groups in a case where a first condition is satisfied.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: October 24, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoya Kamimura
  • Patent number: 9798660
    Abstract: Data exchange between a memory mapped interface and a streaming interface may include receiving sub-packets of a packet from a first interface, storing the sub-packets within a memory at addresses determined according to a ratio of a width of the first interface and a width of a second interface, and determining occupancy, of the memory as the sub-packets are stored. Responsive to determining that the occupancy of the memory meets a trigger level, sub-packets may be read from the memory at addresses determined according to the ratio and sending the sub-packets using the second interface.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: October 24, 2017
    Assignee: XILINX, INC.
    Inventor: Robert Bellarmin Susai
  • Patent number: 9785557
    Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams
  • Patent number: 9779044
    Abstract: A data processor system includes a local memory, a processor core, and an extent monitor. The local memory stores a block of data at a task memory location that is exclusive to a particular task during a duration of time. The processor core accesses the task memory location of the local memory during the execution of the particular task, and modifies to the block of data stored in the task memory location. The extent monitor monitors a write operation the processor core to the local memory to determine a first most-extreme address of the task memory location modified by the execution of the particular task during the duration of time. The processor core also executes a write back instruction to write back to a shared memory location less than the entire block of data based upon the most-extreme address.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: October 3, 2017
    Assignee: NXP USA, Inc.
    Inventor: William C. Moyer
  • Patent number: 9772945
    Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams
  • Patent number: 9766828
    Abstract: A Lock register can be associated with a mailbox. The Lock register can store a claim ID of a process that has allocated the mailbox. The Lock register can include a Lock port and a Lock Clear port, used to claim and release the Lock register. The Lock register only permits data to be written to the Lock Register when the Lock register is not currently allocated, and the Lock Clear port only permits the process that has allocated the Lock register to write a value.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: John H. Hughes, Jr.
  • Patent number: 9760498
    Abstract: An electronic system for multiple agents, both coherent and non-coherent, to communicate with a hybrid cache, the hybrid cache to provide functionality associated with a cache for coherent agents in an outer shareable domain, and to provide functionality associated with a cache for non-coherent agents in a system shareable domain, the functionality provided by tag fields in cache lines stored in the hybrid cache. The tag fields are configured to indicate if a cache line of the hybrid cache belongs to at least one of a logical coherent cache or a logical system cache.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Laurent Rene Moll
  • Patent number: 9740632
    Abstract: In one aspect, a method includes receiving a request to write to an offset in a first logical device, determining a second logical device that wrote to the offset, the second logical device being an ancestor of the first logical device in a hierarchical tree of snapshots, determining from decedents of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data, removing address-to-hash mapping for the offset of the second logical device if the data for the offset is shadowed and moving address-to-hash mapping to a single descendent of the second logical device if the data for the offset is partially shadowed.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 22, 2017
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Phil Love, Kirill Shoikhet, Renen Hallak, Ido Halevi, Irit Lempel
  • Patent number: 9703720
    Abstract: An apparatus and method for efficient guest EPT manipulation. For example, one embodiment of a apparatus comprises: a hypervisor to create extended page table (EPT) mappings between a guest physical address (GPA) space and a host physical address (HPA) space; the hypervisor to create an EPT edit table and populate the EPT edit table with information related to permitted mappings between the GPA space and HPA space; a guest to read the EPT edit table to determine information related to the permitted mappings between the GPA space and HPA space, the guest to use the information to map one or more pages in the GPA space to one or more pages in the HPA space.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventor: Krystof C. Zmudzinski