Patents Examined by Adam M Queler
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Patent number: 10459909Abstract: A system and method for providing mutual exclusivity to an operation is presented. A memory location is checked to determine if the memory location is subject to an exclusive lock. If so, the age of the exclusive lock is determined. If the age of the exclusive lock is greater than a certain length of time, the exclusive lock on the memory location is released such that operations can be performed on the memory location. When a memory lock is created, a length of time can be associated with the memory location. The length of time can be a default length of time. The length of time can be a custom length that is stored in a database. Other embodiments also are disclosed.Type: GrantFiled: January 13, 2016Date of Patent: October 29, 2019Assignee: WALMART APOLLO, LLCInventor: Ergin Guney
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Patent number: 10453530Abstract: System and method for a unified memory and network controller for an all-flash array (AFA) storage blade in a distributed flash storage clusters over a fabric network. The unified memory and network controller has 3-way control functions including unified memory buses to cache memories and DDR4-AFA controllers, a dual-port PCIE interconnection to two host processors of gateway clusters, and four switch fabric ports for interconnections with peer controllers (e.g., AFA blades and/or chassis) in the distributed flash storage network. The AFA storage blade includes dynamic random-access memory (DRAM) and magnetoresistive random-access memory (MRAM) configured as data read/write cache buffers, and flash memory DIMM devices as primary storage. Remote data memory access (RDMA) for clients via the data caching buffers is enabled and controlled by the host processor interconnection(s), the switch fabric ports, and a unified memory bus from the unified controller to the data buffer and the flash SSDs.Type: GrantFiled: March 10, 2015Date of Patent: October 22, 2019Assignee: Futurewei Technologies, Inc.Inventors: Xiaobing Lee, Michael Young, Ting Li, Yansong Wang, Yong Chen
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Patent number: 10437484Abstract: A data protecting method, a memory control circuit unit and a memory storage device are provided. The method includes repeatedly reading data from a first physical programming unit of a first physical erasing unit during an initialization operation after the memory storage device is powered on, wherein the first physical programming unit is the last programmed physical programming unit before the memory storage device is powered off. The method also includes updating a logical-physical mapping table according to the first physical programming unit if a number of error bits of data read each time is not greater than an error bits amount threshold and a reading count of the first physical programming unit is greater than a predetermined count.Type: GrantFiled: March 25, 2016Date of Patent: October 8, 2019Assignee: PHISON ELECTRONICS CORP.Inventor: Kai-Hsiang Yang
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Patent number: 10430347Abstract: An operating system monitors a performance metric of a direct memory access (DMA) engine on an I/O adapter to update a translation table used during DMA operations. The translation table is used during a DMA operation to map a virtual address provided by the I/O adapter to a physical address of a data page in the memory modules. If the DMA engine is being underutilized, the operating system updates the translation table such that a virtual address maps to physical address corresponding to a memory location in a more energy efficient memory module. However, if the DMA engine is over-utilized, the operating system may update the translation table such that the data used in the DMA engine is stored in memory modules that provide quicker access times—e.g., the operating system may map virtual addresses to physical addresses in DRAM rather than phase change memory.Type: GrantFiled: February 25, 2013Date of Patent: October 1, 2019Assignee: International Business Machines CorporationInventor: Justin K. King
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Patent number: 10394719Abstract: A method for replacing data on a volatile memory cache is provided. The volatile memory cache includes one or more memory banks and each of the memory banks includes a plurality of memory lines. The method includes: identifying a replacement ID for at least one of the memory lines to be replaced; identifying a refresh bank ID for one of the memory banks to be refreshed; determining whether or not a conflict exists between the replacement ID and the refresh bank ID; and selecting a new replacement ID if the conflict exists.Type: GrantFiled: March 13, 2017Date of Patent: August 27, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Mu-Tien Chang, Dimin Niu, Hongzhong Zheng
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Patent number: 10387053Abstract: Regions of memory in a distributed computing system may be synchronized. A first computing node may comprise a processor writing to a memory via a memory controller. A request to write data to the memory may be received by the memory controller. The memory controller may send a signal to a logic device which forwards the signal to other computing nodes in the distributed system. The memory controller may detect and respond to conflicting writes by instructing the computing nodes to overwrite conflicting memory regions with a data pattern indicative of the conflict.Type: GrantFiled: September 16, 2015Date of Patent: August 20, 2019Assignee: Amazon Technologies, Inc.Inventor: Andrea Olgiati
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Patent number: 10372617Abstract: A method of applying an address space to data storage in a non-volatile solid-state storage is provided. The method includes receiving a plurality of portions of user data for storage in the non-volatile solid-state storage and assigning to each successive one of the plurality of portions of user data one of a plurality of sequential, nonrepeating addresses of an address space. The address range of the address space exceeds a maximum number of addresses expected to be applied during a lifespan of the non-volatile solid-state storage. The method includes writing each of the plurality of portions of user data to the non-volatile solid-state storage such that each of the plurality of portions of user data is identified and locatable for reading via the one of the plurality of sequential, nonrepeating addresses of the address space.Type: GrantFiled: October 29, 2018Date of Patent: August 6, 2019Assignee: Pure Storage, Inc.Inventors: John Davis, John Hayes, Brian Gold, Shantanu Gupta, Zhangxi Tan
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Patent number: 10289563Abstract: For efficient reclamation of pre-allocated direct memory access (DMA) memory in a computing environment, hot-add random access memory (RAM) is emulated for a general purpose use by reclamation of pre-allocated DMA memory reserved at boot time by notifying a non-kernel use device user that the non-kernel use device has a smaller window, stopping and remapping to the smaller window, and notifying a kernel that new memory has been added, wherein the new memory is a region left after the remap. The hot-add RAM is split into at least two continuous parts.Type: GrantFiled: January 17, 2017Date of Patent: May 14, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shay H. Akirav, Oren Bar, Roman Barsky, Itay Maoz
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Patent number: 10254964Abstract: A system and method for efficiently maintaining metadata stored among a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores at least pairs of a key value and a physical pointer value. The levels are sorted by time. New records are inserted in a created new highest (youngest) level. No edits are performed in-place. A data storage controller determines both a cost of searching a given table exceeds a threshold and an amount of memory used to flatten levels exceeds a threshold. In response, the controller incrementally flattens selected levels within the table based on key ranges. After flattening the records in the selected levels within the key range, the records may be removed from the selected levels. The process repeats with another different key range.Type: GrantFiled: April 30, 2018Date of Patent: April 9, 2019Assignee: Pure Storage, Inc.Inventors: Marco Sanvido, Richard Hankins, Mark McAuliffe, Neil Vachharajani
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Patent number: 10254997Abstract: A backup and archival policy method, system, and non-transitory computer readable medium, includes harnessing of metrics of data classification including both operational data and backup data from an end-to-end stack from a backup Information Lifecycle Governance (ILM) viewpoint.Type: GrantFiled: August 2, 2016Date of Patent: April 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Carmen P. Allen, Jarir Kamel Chaar, Bernhard Julius Klingenberg, Radha P. Ratnaparkhi, Robert Michael Rees, Ramani Ranjan Routray, Dinesh C. Verma
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Patent number: 10248362Abstract: Managing data stored in at least one Data Storage Device (DSD) includes generating a Linear Tape File System (LTFS) write or read command including an LTFS block address. The generated LTFS command is for writing or reading data in an LTFS data partition, writing or reading metadata in the LTFS data partition, or writing or reading metadata in an LTFS index partition. The LTFS block address is translated to a device address for the at least one DSD using state metadata representing a state of the LTFS data partition and/or a state of the LTFS index partition. The data or the metadata is written or read in the at least one DSD at the device address.Type: GrantFiled: July 17, 2017Date of Patent: April 2, 2019Assignee: Western Digital Technologies, Inc.Inventors: James N. Malina, Albert H. Chen
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Patent number: 10235288Abstract: Systems and techniques for cache management are disclosed that provide improved cache performance by prioritizing particular storage stripes for cache flush operations. The systems and techniques may also leverage features of the storage devices to provide atomicity without the overhead of inter-controller mirroring. In some embodiments, the systems and techniques include a storage controller that stores data in a cache. The data is associated with one or more sectors of a storage stripe that is defined over plurality of storage devices. The storage controller identifies a locality of dirty sectors of the one or more sectors, classifies the storage stripe into a category based on the locality, provides a category ordering of the category relative to at least one other category, and flushes the storage stripe from the cache to the plurality of storage devices according to the category ordering.Type: GrantFiled: October 2, 2015Date of Patent: March 19, 2019Assignee: NETAPP, INC.Inventors: Arindam Banerjee, Donald R Humlicek, Scott Terrill
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Patent number: 10235085Abstract: A method for execution by a dispersed storage and task (DST) processing unit that includes a processor includes generating storage unit heat data based on a plurality of temperature readings received from each of a plurality of storage units, where the storage unit heat data indicates a first hot storage unit. A pair of storage units is selected from the plurality of storage units based on the storage unit heat data, where the pair of storage units includes the first hot storage unit and a second storage unit. A data swap request is generated for transmission to the pair of storage units, where the data swap request includes an instruction to transfer at least one first data slice from the first hot storage unit to the second storage unit and to transfer at least one second data slice from the second storage unit to the first hot storage unit.Type: GrantFiled: June 27, 2016Date of Patent: March 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Teague S. Algie, Andrew G. Peake
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Patent number: 10216412Abstract: Operating a data processing system including producing data in the form of plural blocks of data, where each block of data represents a particular region of an output data array, storing the data in a memory of the data processing system, and reading the data from the memory in the form of lines. Storing the data in the memory comprises storing each block of data of a first row of blocks of data in the memory at one or more memory addresses of a first set of memory addresses of a sequence of memory addresses for the memory, and storing each block of data of a second row of blocks of data in the memory at one or more memory addresses of a second set of different memory addresses of the sequence of memory addresses for the memory.Type: GrantFiled: February 14, 2017Date of Patent: February 26, 2019Assignee: Arm LimitedInventor: Sharjeel Saeed
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Patent number: 10191858Abstract: A hypervisor receives, from a guest virtual machine, a request to disable access to a memory range. The hypervisor disables access to the memory range. The hypervisor detects a prohibited access attempt. The prohibited access attempt is an access attempt to the memory range. Responsive to detecting the prohibited access attempt, the hypervisor stops the guest virtual machine. The hypervisor receives a request to reboot the guest virtual machine. The hypervisor reboots the guest virtual machine. Responsive to rebooting the guest virtual machine, the hypervisor enables access to the memory range.Type: GrantFiled: November 25, 2015Date of Patent: January 29, 2019Assignee: Red Hat Israel, Ltd.Inventor: Michael Tsirkin
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Patent number: 10185494Abstract: A method for managing a storage system includes: providing at least one heartbeat monitoring path between a set of expander control circuits within an expansion module in the storage system, for transmitting at least one of a plurality of heartbeat monitoring signals for a set of management modules in the storage system, wherein the expansion module is utilized for installing a set of shared storage devices, and each shared storage device within the set of shared storage devices is coupled to the set of expander control circuits, respectively, to allow the management modules to control the set of shared storage devices through the expander control circuits, respectively. The method further includes performing heartbeat monitoring according to the heartbeat monitoring signals, for at least one of the management modules to perform high availability management on shared storage devices and selectively take over management of non-shared components.Type: GrantFiled: May 24, 2016Date of Patent: January 22, 2019Assignee: Synology IncorporatedInventors: Chi-Lei Ho, Shih-Kai Tsai
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Patent number: 10152266Abstract: The disclosed computer-implemented method for providing data backup services in a virtual environment may include (1) identifying a data path used to transfer, via a storage area network, backup data between a client system and a host operating system of a backup server, (2) establishing communication between the host operating system and a backup agent on a guest operating system of the backup server, and (3) extending the data path to the guest operating system by facilitating data transfer between the host operating system and the backup agent of the guest operating system such that the backup data is transferred between the client system and the backup agent of the guest operating system. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: July 28, 2014Date of Patent: December 11, 2018Assignee: Veritas Technologies LLCInventors: Yingsong Jia, Zhi Su, William Browning
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Patent number: 10140020Abstract: A method for transferring messages from a producer element to a consumer element uses a memory shared between the producer element and the consumer element, and a hardware queue including several registers designed to contain addresses of the shared memory. The method includes the steps of storing each message for the consumer element in the shared memory in the form of a node of a linked list, including a pointer to a next node in the list, the pointer being initially void, writing successively the address of each node in a free slot of the queue, whereby the node identified by each slot of the queue is the first node of a linked list assigned to the slot, and when the queue is full, writing the address of the current node in memory, in the pointer of the last node of the linked list assigned to the last slot of the queue, whereby the current node is placed at the end of the linked list assigned to the last slot of the queue.Type: GrantFiled: February 28, 2017Date of Patent: November 27, 2018Assignee: STMicroelectronics (Grenoble 2) SASInventors: Gilles Pelissier, Jean-Philippe Cousin, Badr Bentaybi
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Patent number: 10133508Abstract: A computer-implemented method for enhancing data protection is disclosed. The method starts with monitoring an operating status of a storage volume at a primary storage of a storage system, where the storage volume is allocated to one or more applications. The method continues with determining whether the operating status of the storage volume satisfies a predetermined condition and notifying a backup application to trigger a backup of the storage volume of the primary storage to a backup storage upon determining that the operating status of the storage volume satisfies the first predetermined condition.Type: GrantFiled: June 13, 2014Date of Patent: November 20, 2018Assignee: EMC IP Holding Company LLCInventors: Stephen D. Smaldone, Jian Xing, Hyong Shim
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Patent number: 10127166Abstract: Techniques are disclosed relating to processing data in a storage controller. In one embodiment, a method includes receiving data at a storage controller of a storage device. The method further includes processing data units of the data in parallel via a plurality of write pipelines in the storage controller. The method further includes writing the data units to a storage medium of the storage device. In some embodiments, the method may include inserting header information into the data for a plurality of data units before processing, and the header information may include sequence information. In some embodiments, writing the data units may include writing according to a sequence determined prior to processing the data units.Type: GrantFiled: April 16, 2014Date of Patent: November 13, 2018Assignee: SanDisk Technologies LLCInventor: James G. Peterson