Patents Examined by Adam M Queler
  • Patent number: 9703504
    Abstract: A storage system includes a plurality of storing devices configured to store data, a cache memory configured to hold data, an access control unit configured to make an access to any one of the plurality of storing devices when an access request for reading of target data or writing of the target data is made from an information processing terminal, and to store the target data in the cache memory, and a writing unit configured to write the target data stored in the cache memory in the storing device which has not stored the target data among the plurality of storing devices.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: July 11, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Takashi Kuwayama
  • Patent number: 9645739
    Abstract: One embodiment provides a computing device. The computing device includes a processor; a chipset; a memory; and indirection logic. The indirection logic is to receive a host logical block address (LBA) associated with a first sector of data, map the host LBA from a host address space to a first device LBA in a device address space, the device address space related to a non-volatile memory (NVM) storage device physical memory address space, and provide the first sector of data and the first device LBA to the NVM storage device.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 9, 2017
    Assignee: INTEL CORPORATION
    Inventors: Bryan E. Veal, Dan J. Williams, Annie Foong
  • Patent number: 9639469
    Abstract: A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store.
    Type: Grant
    Filed: July 13, 2013
    Date of Patent: May 2, 2017
    Assignee: Qualcomm Technologies, Inc.
    Inventors: Laurent Moll, Jean-Jacques Lecler, Jonah Proujansky-Bell
  • Patent number: 9588902
    Abstract: A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: March 7, 2017
    Assignees: Advanced Micro Devices, Inc., ATI Technologies, ULC
    Inventors: Elene Terry, Dhirendra Partap Singh Rana
  • Patent number: 9582423
    Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: February 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Jose E. Moreira
  • Patent number: 9582424
    Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: February 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Jose E. Moreira
  • Patent number: 9575827
    Abstract: A non-transitory computer-readable recording medium stores a memory management program that causes a computer to execute a process. The process includes detecting writing into a memory; and saving, in association with each other in a predetermined storage area, data before the writing which is stored in a data area of a write destination of the detected writing, and context information of a processor at a time of detecting the writing into the memory.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: February 21, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Masayuki Jibu, Kentaro Nishihara, Yuki Hasegawa, Kazuya Watanabe, Kazuhide Imaeda, Hiroyuki Yamamoto, Yasutoshi Suzuki
  • Patent number: 9558112
    Abstract: A data storage device includes multiple flash memory devices with each of the flash memory devices being arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices. The memory controller is configured to mark one or more of the pages of the flash memory devices as available for deletion and maintain the marked pages as available for being read until deleted during garbage collection.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: January 31, 2017
    Assignee: Google Inc.
    Inventor: Albert T. Borchers
  • Patent number: 9552174
    Abstract: Systems and methods for reducing problems and disadvantages associated with protecting data during cold excursions are provided. A method for preventing unreliable data operations at cold temperatures may include determining whether a first temperature of a solid state drive (SSD) is below a threshold temperature. The method may also include initiating an artificial read/write operation if the first temperature is below the threshold temperature.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: January 24, 2017
    Assignee: Dell Products L.P.
    Inventor: Clinton Allen Powell
  • Patent number: 9547597
    Abstract: A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: January 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bartholomew Blaner, David W. Cummings, Brian Flachs, Michael S. Siegel, Jeffrey A. Stuecheli
  • Patent number: 9519588
    Abstract: Cache lines of a data cache may be assigned to a specific page type or color. In addition, the computing system may monitor when a cache line assigned to the specific page color is allocated in the cache. As each cache line assigned to a particular page color is allocated, the computing system may compare a respective index associated with each of the cache lines to determine maximum and minimum indices for that page color. These indices define a block of the cache that stores the data assigned to the page color. Thus, when the data of a page color is evicted from the cache, instead of searching the entire cache to locate the cache lines, the computing system uses the maximum and minimum indices as upper and lower bounds to reduce the portion of the cache that is searched.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: December 13, 2016
    Assignee: CISCO TECHNOLOGY, INC.
    Inventor: Donald Edward Steiss
  • Patent number: 9489228
    Abstract: A method and system for managing a virtual computing system including a hypervisor managing a virtual machine (VM) configured to communicate with a thread executable by multiple host central processing units (CPUs), using memory monitoring instructions. The hypervisor provides the virtual machine with a first notification identifying a first designated memory range writeable by a virtual central processing unit (VCPU) associated with the virtual machine and a first instruction to write to the first designated memory range to communicate with the thread running on a first host CPU. The hypervisor further identifies movement of the thread from the first host CPU to a second host CPU and provides to the virtual machine a second notification identifying a second designated memory range and a second instruction to write to the second designated memory range to communicate with the thread running on the second host CPU.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: November 8, 2016
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Avi Kivity, Dor Laor
  • Patent number: 9489141
    Abstract: In an all-flash storage array, write requests can take about 9 to 10 times longer than a read request of the same size. There could be several problems when reading or writing from all-flash storage, such as a large write request slowing down small read requests, or other write requests. Also, a large read request may slow down smaller read requests by filling the incoming requests queue. In one implementation, a determination is made on what is the maximum size of a request to flash storage that improves the throughput of a flash chip (e.g., write requests beyond a certain size do not improve throughput). A chunklet is defined as a block of data having the calculated maximum size. As write requests come in, the write requests are broken into chunklets, and then the chunklets are queued for processing by the flash chip. One chunklet is processed at a time per write request.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 8, 2016
    Assignee: Nimble Storage, Inc.
    Inventors: Anil Kumar Nanduri, Murali Krishna Vishnumolakala
  • Patent number: 9459806
    Abstract: For combining virtual mapping metadata and physical space mapping metadata in a storage system by a processor device in a computing environment, data and metadata are maintained into separate virtual streams. The separate virtual streams include a metadata stream for the metadata and a data stream for the data. Metadata for each input/output (I/O) operation received is determined using a linear function operation, the function operation being an offset of the metadata in the metadata stream that is equal to the I/O operation multiplied by a maximal metadata ratio. The metadata is allocated on the metadata stream and the metadata stream is divided into fixed size block that is responsible for describing a size of a logical space, where the logical space is equal to one divided by the maximal metadata ratio, and it is determined if the metadata has been previously loaded.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: October 4, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yuval Berger, Ben Sasson, Ori Shalev, Yosef Shatsky
  • Patent number: 9459999
    Abstract: A memory control method for a computer system is provided. The method includes the steps of: (a) calculating an operation cost of each of given M memory objects in each of N memory regions, M being an integer larger than 0, wherein the operation cost is a quantifiable parameter of a said memory region with respect to a said memory object operating therein; (b) determining an optimized allocation of the M memory objects in the N memory regions according to the calculated operation cost of each of the M memory objects in each of the N memory regions.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: October 4, 2016
    Assignee: International Business Machines Corporation
    Inventors: Chun-Wei Chen, Jenseng J S Chen, Albert Lee, Alex C P Lee, Kelvin Shieh
  • Patent number: 9454493
    Abstract: Systems and methods for verifying the wiping of a storage device using one of either a partial scan verification or a full scan verification, wherein a partial scan verification may be conducted based on at least one metric associated with the storage device and a threshold value for the at least one metric.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: September 27, 2016
    Assignee: Amazon Technologies, Inc.
    Inventor: Eden G. Adogla
  • Patent number: 9442809
    Abstract: According to the present invention, it is possible to construct a backup configuration of a particular application data, without influencing data of another application. A management computer is coupled to a host computer on which an application operates, and to a storage apparatus that includes a plurality of volume groups each having one or more logical volumes. At least one of the logical volumes is allocated to the application. The management computer includes a volume group overlapping use determination part and a backup policy determination part. When the backup of the volume group to which one logical volume belongs is configured, the volume group overlapping use determination part determines whether there is another application that uses the volume group. The backup policy determination part determines whether there is set, for another volume group, backup policy information same as that set for the application.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: September 13, 2016
    Assignee: HITACHI, LTD.
    Inventors: Misako Irisawa, Nobuhiro Maki, Masayasu Asano, Wataru Okada
  • Patent number: 9442666
    Abstract: Embodiments of the invention are directed to optimizing reconstruction of operation data in volatile memory of solid-state storage subsystems. In various embodiments, operation data is stored in the volatile memory with persistent backup data of the operation data in the non-volatile memory. In one embodiment, operation data includes a superblock table that is used to identify most or all groups of blocks (superblocks) within the storage device that certain firmware components operate on. Sometimes operation data in the volatile memory is lost or corrupted due to a power interruption or system shutdown. To optimize the reconstruction of the superblock table or other similar operation data in the volatile memory, embodiments of the invention use a “snapshot entry” to identify the latest entry information, allowing the controller to quickly identify the most updated physical locations of the operation data portions and complete the reconstruction in an efficient manner.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 13, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lyndon S. Chiu, Jerry Lo
  • Patent number: 9430367
    Abstract: A first RAID module is added to a first RAID controller and a second RAID module is added to a second RAID controller. An array of physical disks is partitioned into two partitions across the array of physical disks. The first partition is assigned to the first RAID module and the second partition is exposed to the second RAID module. Each of the RAID modules exposes their respective partitions to their associated RAID controller as a single array. Each RAID module further receives I/O from its respective RAID controller, and translates the I/O to access its associated partition.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: August 30, 2016
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Srikumar Subramanian, Senthilkumar Ramasamy, Loganathan Ranganathan, Udita Chatterjee
  • Patent number: 9411735
    Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Jose E. Moreira