Abstract: The present invention provides a single crystal wafer, wherein the main surface has a plane or a plane equivalent to a plane tilting with respect to a [100] axis of single crystal by angles of ? (0°<?<90°) for the [011] direction, ? (0°<?<90°) for the [01-1] direction and ? (0°??<45°) for the [10-1] or [101] direction. Thus, a single crystal wafer that can sufficiently bear device production processes even with a small wafer thickness is provided and thereby loss of single crystal raw material is reduced. Further, by using such a wafer, MIS type semiconductor devices and solar cells are provided at a low cost.

Abstract: In order to prevent irreversible deformation of column-shaped spacers which retain the gap between a pair of substrates between which the liquid crystal layer of a liquid crystal display device is interposed, spacers which assist in preventing such irreversible deformation are newly provided. According to the invention, two or more kinds of spacers which differ in height from a reference surface are disposed on one of the pair of substrates. In addition, a step pattern with which the spacers are to come into contact is formed in advance on the other of the pair of substrates so that the heights of the spacers can be made different.

Abstract: A liquid crystal display device includes a substrate, a gate electrode disposed on the substrate, a gate pad disposed on the substrate, an insulating film disposed on the gate electrode and the gate pad, an active layer disposed on the insulating film above the gate electrode, an ohmic contact layer disposed on portions of the active layer, a source electrode and a drain electrode disposed on the ohmic contact layer, a passivation layer disposed on the source and drain electrodes, a pixel electrode disposed on the passivation layer and contacting the drain electrode, and a transparent electrode disposed on the passivation layer and contacts the gate pad, wherein the gate electrode and the gate pad both include a first layer formed of a first metal and a second layer formed of an alloy of the first metal and a second metal disposed at an upper surface of the first layer.

Abstract: An unstable factor that the orientation of liquid crystal is fixed and left after a drive power source is turned off is reduced, preferable display quality is realized, and long term reliability is improved. After the drive power source is turned off, in order to block an electric field produced by charges left in a first electrode (485), a second electrode 492 is provided to overlap the first electrode. The first electrode is overlapped at 70% or more of its area with the second electrode. In addition, when the first electrode is used as an electrode composing a retaining capacitor 505, the retaining capacitor is overlapped at 90% or more of its area with the second electrode.

Abstract: A light-emitting device is disclosed as typified by a laser oscillator formed by an electroluminescent material with improved oscillation efficiency of laser light and even reduced power consumption. The disclosed light-emitting device comprises a light-emitting element including a first electrode having a concave portion, an electroluminescent layer serving as a laser medium formed over the first electrode so as to be overlapped with the concave portion, and a second electrode formed over the electroluminescent layer so as to be overlapped with the concave portion, wherein light generated in the electroluminescent layer is resonated between the first electrode and the second electrode and emitted as laser light from the second electrode, an optical axis of the laser light intersects with the second electrode, the first electrode has a curved surface at the concave portion, and a center of curvature of the curved surface is located at the side of the second electrode above the first electrode.

Abstract: A thin film transistor (TFT) including a semiconductor film that may be simply patterned, a method of manufacturing the TFT, a flat panel display (FPD) including the TFT, and a method of manufacturing the FPD. The TFT includes a gate electrode, source and drain electrodes electrically insulated from the gate electrode, and a semiconductor film electrically insulated from the gate electrode and including source and drain regions coupled to the source and drain electrodes, respectively, and a channel region coupling the source and drain regions. The semiconductor film has a groove that isolates the channel region from an adjacent TFT.

Abstract: To provide an organic EL device capable of making uniform a dry speed of a liquid material coated in a display area. There is provided an organic EL device in which a plurality of pixels XR, XG, XB is arranged in an effective display area of a substrate and each of the pixels XR, XG, XB is provided with a first organic EL element having a functional film formed by a liquid phase method, wherein a dummy area D having a plurality of dummy pixels D1R, D1G, D1B, D2R, D2G, D2B for inspection of characteristics is provided around the effective display area and each dummy pixel is provided with a second organic EL element having a functional film formed using the same process as the functional film of the first organic EL element.

Abstract: Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on the first insulating layer in a predetermined shape, including source and drain electrodes separated by a predetermined interval; a second insulating layer located on the semiconductor layer between the source and drain electrodes; a memory layer, which is deposited on sides of a portion of the semiconductor layer between the source and drain electrodes and on sides and an upper surface of the second insulating layer, including electron transferring channels and an electron storing layer; and a gate electrode, which is deposited on a surface of the memory layer, for controlling transfer of electrons in the memory layer. The programming method may provide a large capacity, stable, multi-level memory.

Abstract: An integrated circuit includes a field plated resistor having enhanced area thereover for routing metal conductors, formed in the same layer of metal as forms contacts to the resistor, is fabricated by a sequence of processing steps. A resistor having a resistor body and a contact region at each end thereof is formed in an active region of a semiconductor substrate. A first layer of insulative material is formed over the resistor and a window is created through the first layer of insulative material to the resistor body to form a first contact region. A layer of polysilicon is formed over the first insulative layer to define a field plate, the polysilicon field plate being contiguous with the first contact region of the resistor and extending over the resistor body to substantially to the other contact region, as layout, design, and fabrication rules permit. A second insulative layer is formed over the polysilicon layer.

Abstract: A semiconductor chip for optoelectronics having a thin-film layer, in which a zone that emits electromagnetic radiation is formed and which has an emission side, a rear side and side faces that connect the rear side to the emission side. A carrier for the thin-film layer is arranged at the rear side thereof and is connected thereto. At least one electrical front side contact structure is formed on the emission side and at least one trench is formed on the rear side. The trench defines at least a single partial region which essentially does not overlap the front side contact structure.

Abstract: A optoelectronic semiconductor device, mountable on and electrically connectable to an electro-optical wiring board, a substrate thereof having a light input/output through-hole and electric connection through-holes, the light input/output through-hole being not formed in a stressed area of the circuit wiring board, but formed in a non-stressed area of the circuit wiring board, the stressed area being an area where a stress is larger in value than the mean value of stresses caused in the circuit wiring board by a difference in coefficient of thermal expansion between the circuit wiring board and the electro-optical wiring board when the electrode on the semiconductor optoelectronic device is mechanically fixed to and electrically connected to the electro-optical wiring board.

Abstract: Provided are a CMOS image sensor in which microlenses are formed in a remaining space in a patterned light shielding layer to improve image sensor characteristics and to protect the microlenses during packaging, and a method of fabricating the same. The CMOS image sensor may include: a semiconductor substrate; at least one photodiode on or in the semiconductor substrate; a first insulating layer on the substrate including the photodiode(s); a plurality of metal lines on and/or in the first insulating layer; a second insulating layer on the first insulating layer including at least some of the metal lines; a patterned light shielding layer on the second insulating layer; and microlenses in a remaining space on the second insulating layer.

Abstract: The invention relates to an electronic component and a semiconductor wafer, and a method for producing them. The semiconductor wafer has strip-type separating regions. The separating regions are provided with through contacts in the direction of the rear side of the semiconductor wafer. The semiconductor chip separated from such a semiconductor wafer constitutes an electronic component with external contacts in the form of edge contacts. Such an electronic component of semiconductor chip size can be used in diverse ways.

Abstract: In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

Abstract: The present invention discloses a high-speed flat panel display with a long lifetime, wherein thin film transistors in a pixel array portion in which a plurality of pixels are arranged and a driving circuit portion for driving the pixels of the pixel array portion, have different resistance values than each other or have different geometric structures than each other. The flat panel display comprises a pixel array portion where a plurality of pixels are arranged, and a driving circuit portion for driving the pixels of the pixel array portion. The thin film transistors in the pixel array portion and the driving circuit portion have different resistance values in their gate regions or drain regions than each other, or have different geometric structures than each other. One of the thin film transistors in the pixel array portion and the thin film transistors in the driving circuit has zigzag shape in its gate region or drain region or has an offset region.

Abstract: Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a groove formed in the active region. A field oxide layer is formed on the substrate around the active region in such a manner that it has a surface lower than the upper surface of the active region including the groove. A pair of gates are placed along one and the other ends of groove across the upper surface of the active region while overlapping the stepped portion of the active region. The transistor has the structure of a step-gated asymmetry transistor when seen in a sectional view taken in a first direction, as well as that of a fin transistor when seen in a sectional view taken in a second direction, which is perpendicular to the first direction.

Abstract: A quantum coherent switch having a substrate formed from a density wave (DW) material capable of having a periodic electron density modulation or spin density modulation, a dielectric layer formed onto a surface of the substrate that is orthogonal to an intrinsic wave vector of the DW material; and structure for applying an external spatially periodic electrostatic potential over the dielectric layer.

Abstract: In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.

Abstract: A semiconductor integrated circuit structure includes a plurality of diodes disposed in the substrate. These diodes are electrically coupled in series. At least one insertion region is disposed in the substrate between two of the diodes and a supply voltage node electrically coupled to the insertion region. Preferably, a guard ring surrounds the diodes.

Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor.