Patents Examined by Ajay Arora
  • Patent number: 12224296
    Abstract: An image sensor includes: a semiconductor substrate that has a first surface and a second surface opposite to each other. The semiconductor substrate includes: a first trench that vertically extends from the first surface of the semiconductor substrate and provides a pixel region, and a second trench that vertically extends from the first surface of the semiconductor substrate and is disposed on the pixel region. The image sensor further includes: a pixel separation structure that vertically extends from the second surface of the semiconductor substrate and overlaps the first trench; and a gap-fill dielectric layer disposed on the first surface of the semiconductor substrate, wherein the gap-fill dielectric layer includes a pixel separation part and a scattering pattern part, wherein the pixel separation part is disposed in the first trench, and the scattering pattern part is disposed in the second trench.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: February 11, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hongki Kim, Changrok Moon, Taehyong Kim, Seungjae Oh, Jihyun Kwak
  • Patent number: 12224228
    Abstract: A method for manufacturing a packaged component with a composite pin structure has: dividing a substrate into a body area and a pin area, wherein a chip is arranged on the body area of the substrate and is electrically connected to conductive layers on the opposite surfaces of the substrate. The pin area is pre-defined with multiple parallel pin positions. After the electrical connection of the chip is completed in the body area, a cutting tool is used to cut along the peripheries of the body area and the pin positions to obtain a packaged component body and multiple pins. Each of the pins is integrally formed by the substrate of the packaged component body without using a conventional lead frame.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: February 11, 2025
    Assignee: PANJIT INTERNATIONAL INC.
    Inventors: Yung-Hui Wang, Chung-Hsiung Ho, Chi-Hsueh Li
  • Patent number: 12218048
    Abstract: A method of constructing a superconducting switch includes depositing a thin sacrificial layer on top of a substrate. The sacrificial layer is patterned to remove portions of the sacrificial layer except at a first portion of the substrate. A superconducting metal layer is patterned on top of the substrate and on top of the sacrificial layer. The superconducting metal layer is patterned to form a superconducting metal line over the sacrificial layer. The patterned sacrificial layer is etched from under the superconducting metal line to release the metal line from the substrate.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: February 4, 2025
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vivekananda P. Adiga, Russell A. Budd, Charles Thomas Rettner, Stephen M. Gates
  • Patent number: 12219832
    Abstract: According to one embodiment, a flexible substrate includes an insulating base including first and second strip portions, and island-shaped portions, electrical elements, scanning lines each extending while overlapping the first strip portions, signal lines each extending while overlapping the second strip portions, connection wiring lines each extending while overlapping the second strip portions, a scanning line driver, a signal line driver, a support body including a first side edge, and scanning lines are connected to different connection wiring lines on different island-shaped portion, and the scanning line driver and the signal line driver are located on a side of the first side edge.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 4, 2025
    Assignee: Japan Display Inc.
    Inventor: Takumi Sano
  • Patent number: 12218031
    Abstract: Systems and methods of providing a bare circuit integrated circuit package with a containment ring are described. The bare circuit integrated circuit package may be provided with a substrate connected to a printed circuit board. An integrated circuit may be connected to the substrate. A stiffener ring that surrounds the integrated circuit may be attached to the substrate. A heat sink may be positioned on the stiffener ring and over the integrated circuit such that there is a space between a top of the integrated circuit and a bottom surface of the heat sink. A thermal interface material may be provided to thermally connect the integrated circuit and the heat sink. A containment ring may be positioned between the stiffener ring and the integrated circuit, the containment ring sized and positioned to prevent pumping and/or displacement of the thermal interface material.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: February 4, 2025
    Assignee: Infinera Corporation
    Inventors: John W. Osenbach, Gannon Reichert, Vinh Nguyen
  • Patent number: 12191227
    Abstract: Provided is a heat dissipating substrate including a diamond substrate, wherein an upper portion of the diamond substrate has a concave-convex structure including recessed regions that are spaced apart from each other, and insulation patterns that fill the recessed regions. The insulation patterns include at least one of silicon carbide, silicon nitride, silicon oxide, aluminum nitride, and aluminum oxide.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: January 7, 2025
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyung Seok Lee, Sung-Bum Bae
  • Patent number: 12191218
    Abstract: A semiconductor device includes a semiconductor element, a heat sink on which the semiconductor element is mounted, and a case made of resin, the case being mounted on the heat sink and containing the semiconductor element. A fastening hole is formed passing through the case and the heat sink. The case includes a surface pressure absorbing member on a portion including the fastening hole in plan view, the surface pressure absorbing member having a plate shape and being higher in rigidity than the resin.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: January 7, 2025
    Assignee: Mitsubishi Electric Corporation
    Inventors: Arata Iizuka, Korehide Okamoto
  • Patent number: 12191223
    Abstract: The semiconductor device includes a supporting member, a conductive member, and a semiconductor element. The supporting member has a supporting surface facing in a thickness direction. The conductive member has an obverse surface facing the same side as the supporting surface faces in the thickness direction, and a reverse surface opposite to the obverse surface. The conductive member is bonded to the supporting member such that the reverse surface faces the supporting surface. The semiconductor element is bonded to the obverse surface. The semiconductor device further includes a first metal layer and a second metal layer. The first metal layer covers at least a part of the supporting surface. The second metal layer covers the reverse surface. The first metal layer and the second layer are bonded to each other by solid phase diffusion.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: January 7, 2025
    Assignee: ROHM CO., LTD.
    Inventor: Xiaopeng Wu
  • Patent number: 12191421
    Abstract: A light emitting substrate and a display device are provided, the light emitting substrate includes: a base substrate: an electrode planarization layer, on the base substrate: an electrode layer, at a side of the electrode planarization layer away from the base substrate, the electrode layer includes a first electrode and a second electrode, the first electrode includes at least one first electrode strip, the second electrode includes at least one second electrode strip, the first electrode strip and the second electrode strip are spaced and alternately arranged in a first direction, each of the at least one first electrode strip and each of the at least one second electrode strip extend along a second direction, the electrode planarization layer includes a first groove between a first electrode strip and a second electrode strip which are adjacent to each other, the first groove is configured to accommodate a light emitting diode.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: January 7, 2025
    Assignees: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunping Long, Qi Qi, Xinxin Zhao, Wanzhi Chen
  • Patent number: 12183645
    Abstract: An electronic component includes a substrate, a functional element on the substrate, a support body, a covering portion, and a protective layer covering the covering portion. The support body is provided on the substrate and around a region in which the functional element is located. The covering portion faces the substrate and is supported by the support body. The substrate, the support body, and the covering portion define a hollow space. The functional element is located in the hollow space. In the support body, a surface opposite to a surface facing the substrate is a first surface, and a portion of the protective layer is in contact with the first surface of the support body without the covering portion being interposed.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: December 31, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazunori Inoue, Shintaro Otsuka, Koichiro Kawasaki, Hidefumi Nakanishi, Masakazu Atarashi, Masahiro Fukushima
  • Patent number: 12166149
    Abstract: A light-emitting diode 100 includes a first region 1, for example of the P type, formed in a first layer 10 and forming, in a direction normal to a basal plane, a stack with a second region 2 having at least one quantum well formed in a second layer 20, and including a third region 3, for example of the N type, extending in the direction normal to the plane, bordering and in contact with the first and second regions 1, 2, through the first and second layers 10, 20. A process for producing a light-emitting diode 100 in which the third region 3 is formed by implantation into and through the first and second layers 10, 20.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: December 10, 2024
    Assignee: ALEDIA
    Inventors: Ivan-Christophe Robin, Xavier Hugon, Philippe Gilet, Tiphaine Dupont
  • Patent number: 12159828
    Abstract: Provided are a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes: a through silicon via and a shielding structure disposed at an outer side of the through silicon via, in which the shielding structure includes at least two non-closed annular shielding layers surrounding the through silicon via and at least one conductive plug configured to connect two adjacent ones of the non-closed annular shielding layers; the at least two non-closed annular shielding layers and the at least one conductive plug are alternately distributed along an extending direction of the through silicon via and sequentially connected to form a conductive path, and current flow directions in two adjacent ones of the non-closed annular shielding layers in the conductive path are opposite.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 3, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tzung-Han Lee, Chih-Cheng Liu
  • Patent number: 12154866
    Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: November 26, 2024
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo
  • Patent number: 12154836
    Abstract: According to one embodiment, a semiconductor device includes a first container and a second container. The second container is inside the first container. A semiconductor element is inside the second container. The second container is formed of a lower portion, a side portion fixed to the lower portion, and an upper portion fixed to the side portion and the first container. The side portion is a first metal material covered with a first insulator. The lower portion and the side portion of the second container are spaced from the first container. The semiconductor device may be used as a power module or the like in some instances, and the semiconductor element may be one or more transistors of the like.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: November 26, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hisashi Tomita
  • Patent number: 12148815
    Abstract: A fin field effect transistor device structure includes a substrate, an isolation structure, a first fin structure, a fin top layer, a first oxide layer, and a first gate structure. The first fin structure is disposed in the substrate and includes a base portion, a top portion, and a joint portion. The base portion is surrounded by the isolation structure. The top portion is exposed from the isolation structure. The joint portion connects the top portion and the base portion. The fin top layer is disposed over the top portion of the first fin structure. The fin top layer and the top portion of the first fin structure are made of different materials. The first oxide layer covers the fin top layer, the first fin structure, and the isolation structure. The first gate structure is disposed over the first oxide layer.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Shi-Ning Ju, Chih-Hao Wang
  • Patent number: 12142559
    Abstract: A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: November 12, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Yuma Murata
  • Patent number: 12132008
    Abstract: Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: October 29, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Patent number: 12132005
    Abstract: Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: October 29, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Patent number: 12131981
    Abstract: Implementations described herein are related to a semiconductor device package having an improved baseplate. In such an improved baseplate, there is a recess cut out of a region of a surface of the baseplate such that the recess has a first sidewall having a first thickness above a recess base and a second sidewall having a second thickness above the recess base. A substrate, e.g., a direct bonded copper (DBC) substrate, may be attached to the baseplate at a recess base using, e.g., a solder layer between the recess base and a surface of the substrate.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: October 29, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yushuang Yao, Vemmond Jeng Hung Ng
  • Patent number: 12125758
    Abstract: A power semiconductor device in which the size of an insulating substrate is reduced and connection failure can be suppressed includes an insulating substrate, a semiconductor element, and a printed circuit board. The semiconductor element is bonded to one main surface of the insulating substrate. The printed circuit board is bonded to face the semiconductor element. The semiconductor element has a main electrode and a signal electrode. The printed circuit board includes a core member, a first conductor layer, and a second conductor layer. The second conductor layer has a bonding pad. The printed circuit board has a missing portion. A metal column portion is arranged to pass through the inside of the missing portion and reach the insulating substrate. The signal electrode and the bonding pad are connected by a metal wire. The metal column portion and the insulating substrate are bonded.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: October 22, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuhiro Asaji, Kazuya Okada, Hidetoshi Ishibashi