Abstract: The semiconductor device includes a supporting member, a conductive member, and a semiconductor element. The supporting member has a supporting surface facing in a thickness direction. The conductive member has an obverse surface facing the same side as the supporting surface faces in the thickness direction, and a reverse surface opposite to the obverse surface. The conductive member is bonded to the supporting member such that the reverse surface faces the supporting surface. The semiconductor element is bonded to the obverse surface. The semiconductor device further includes a first metal layer and a second metal layer. The first metal layer covers at least a part of the supporting surface. The second metal layer covers the reverse surface. The first metal layer and the second layer are bonded to each other by solid phase diffusion.

Abstract: A TMR element includes a magnetic tunnel junction, a side wall portion that covers a side surface of the magnetic tunnel junction, and a minute particle region that is disposed in the side wall portion. The side wall portion includes an insulation material. The minute particle region includes the insulation material and a plurality of minute magnetic metal particles that are dispersed in the insulation material. The minute particle region is electrically connected in parallel with the magnetic tunnel junction.

Abstract: A semiconductor package includes a chip package disposed on a substrate, a plurality of electronic components disposed aside the chip package on the substrate and a stiffener structure disposed on the substrate. The stiffener structure includes a stiffener ring surrounding the chip package and the plurality of electronic components, a stiffener rib between the chip package and the plurality of electronic components, wherein the stiffener rib includes a first portion and a second portion on the first portion, and a width of the second portion is greater than a width of the first portion. The semiconductor package further includes a lid attached to the stiffener structure, the chip package and the plurality of electronic components. A method of forming the semiconductor package is also provided.

Abstract: A semiconductor device A1 includes a semiconductor element 10A having an element obverse face 101 and an element reverse face 102, the element obverse face 101 having an obverse face electrode 11 formed thereon and the element reverse face 102 having a reverse face electrode 12 formed thereon, a conductive substrate 22A including an obverse face 221A opposed to the element reverse face 102, and to which the reverse face electrode 12 is conductively bonded, a conductive substrate 22B including an obverse face 221B and spaced from the conductive substrate 22A in a width direction x, and a lead member 51 extending in the width direction x, and electrically connecting the obverse face electrode 11 and the conductive substrate 22B. The lead member 51 is located ahead of the obverse face 221B in the direction in which the obverse face 221B is oriented, and bonded to the obverse face electrode 11 via a lead bonding layer 32.

Abstract: There is provided a terminal that includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer which is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.

Abstract: The present disclosure provides an OLED display motherboard and a method for manufacturing the same, a method for manufacturing the OLED display panel, and an OLED display device thereof. The OLED display motherboard includes a base substrate having a display region and a non-display region surrounding the display region, a TFT and an OLED device located within the display region of the base substrate, at least two crack stop slits located within the non-display region of the base substrate, an extending direction of the crack stop slit being the same as an extending direction of an edge of the display region of the base substrate, and adjacent crack stop slits being separated by a crack stop slit step, and an encapsulation layer covering the crack stop slit and the OLED device. A portion of the encapsulation layer has a non-uniform thickness.

Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.

Abstract: Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed.

Abstract: Curable material layer is coated on surface of first die. First die includes first substrate and first contact pad. Second die is bonded to first die. Second die includes second substrate and second contact pad. Second contact pad is located on second substrate, at an active surface of second die. Bonding the second die to the first die includes disposing second die with the active surface closer to the curable material layer and curing the curable material layer. A through die hole is etched in the second substrate from a backside surface of the second substrate opposite to the active surface. The through die hole further extends through the cured material layer, is encircled by the second contact pad, and exposes the first contact pad. A conductive material is disposed in the through die hole. The conductive material electrically connects the first contact pad to the second contact pad.

Abstract: A display apparatus includes a flexible substrate, a thin-film transistor unit, and a light-emitting unit. The flexible substrate includes a display area has a first area, a peripheral area which is adjacent to the display area, and a first penetrating portion corresponding to the first area. The thin-film transistor unit is in the display area and at least a portion of the peripheral area. The thin-film transistor unit includes a thin-film transistor and an insulation layer and has a second penetrating portion at a location corresponding to the first penetrating portion. The light-emitting unit is on the thin-film transistor unit and includes a pixel electrode, an intermediate layer including an emission layer, and a counter electrode.

Abstract: A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body and having body regions of a first conductivity type, a drift region of a second conductivity type that is opposite from the first conductivity type and is disposed between the body regions and a second surface of the semiconductor body that is opposite from the first surface, and an emitter layer of the second conductivity type that is disposed between the drift region and a second surface of the semiconductor body, the emitter layer having a higher dopant concentration than the drift region, a metal drain electrode directly adjoining the emitter layer. The metal drain electrode comprises spikes extending into the emitter layer.

Abstract: A power semiconductor device includes a die carrier, a power semiconductor chip coupled to the die carrier by a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier by a second solder joint, and a sealing mechanically attaching the sleeve to the die carrier, the sealing being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the sealing does not cover the power semiconductor chip.

Abstract: A package includes an electronic component, an inorganic encapsulant encapsulating at least part of the electronic component, and an adhesion promoter between at least part of the electronic component and the encapsulant.

Abstract: The present technology relates to a solid-state image pickup element, electronic equipment, and a semiconductor apparatus that make it possible to reduce a surface reflection in an area in which a slit is formed and improve flare characteristics. A solid-state image pickup element includes a pixel area in which a plurality of pixels is two-dimensionally arranged in a matrix, a chip mounting area in which a chip is flip-chip mounted, and a dam area that is arranged around the chip mounting area and in which one or more slits that block an outflow of a resin are formed. In the dam area, the same OCL as that in the pixel area is formed. The present technology can be applied to a solid-state image pickup element etc. in which a chip is flip-chip mounted, for example.

Abstract: An object is to provide a technique capable of regulating a direction in which an adhesive agent used for bonding a base plate and a case is wetly widened. A semiconductor device includes a base plate and a case. The case is bonded to a peripheral edge part of the base plate via an adhesive agent. A dip which is an application position where the adhesive agent is applied and an inclined surface directed downward from the dip toward an outer peripheral side or an inclined surface directed downward from the dip toward an inner peripheral side are formed in the peripheral edge part of the base plate.

Abstract: An object of the present invention is to provide a semiconductor device in which the effect of dimensional tolerance can be reduced, and a method for manufacturing the same. The semiconductor device according to the present invention includes: a plurality of cooling plates each having a coolant passage inside; spacers disposed to stack the cooling plates with spaces; at least one semiconductor package disposed on at least one principal surface of at least one of the cooling plates; and a spring plate disposed between adjacent ones of the cooling plates, the spring plate biasing the at least one semiconductor package toward the cooling plates.

Abstract: The present disclosure provides a semiconductor device with air gaps between adjacent conductive lines and a method for forming the semiconductor device. The semiconductor device with air gaps between adjacent conductive lines and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode.

Abstract: According to an aspect of the disclosure, an example microelectronic device assembly includes a substrate, a microelectronic element electrically connected to the substrate, a stiffener element overlying the substrate, and a heat distribution device overlying the rear surface of the microelectronic element. The stiffener element may extend around the microelectronic element. The stiffener element may include a first material that has a first coefficient of thermal expansion (“CTE”). A surface of the stiffener element may face toward the heat distribution device. The heat distribution device may include a second material that has a second CTE. The first material may be different than the second material. The first CTE of the first material of the stiffener element may be greater than the second CTE of the second material of the heat distribution device.

Abstract: A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key.

Abstract: A display substrate and a preparation method thereof, and a display panel are provided. The display substrate includes at least one first sub-pixel and at least one second sub-pixel, the first sub-pixel and the second sub-pixel have different display directions, the first sub-pixel includes a first light-emitting element, the second sub-pixel includes a second light-emitting element, each of the first light-emitting element and the second light-emitting element has a light-emitting structure, the light-emitting structure includes a first reflective layer, a light emitting layer and a second reflective layer which are sequentially stacked, the second reflective layer is located on a light emergent side of the display substrate, and an area of the first reflective layer is larger than an area of the second reflective layer.