Abstract: An external contact element for a power semiconductor module includes a bonded blank strip, the bonded blank strip being formed such that the external contact element includes: a first contact portion configured to be coupled to the power semiconductor module by a first solder joint, a second contact portion spaced from the first contact portion in a thickness direction out of the plane of the first contact portion, the second contact portion being configured to be coupled to an external appliance, and a spring portion connecting the first and second contact portions to each other and configured to compensate a movement along the thickness direction. The bonded blank strip includes a first sheet of a first metal or first metal alloy and a second sheet of a different second metal or second metal alloy. The second sheet is omitted from at least a substantial part of the first contact portion.

Abstract: An object is to provide a semiconductor device in which heat generated in a lead electrode when conducting a large current can be reduced and the bonding quality between the lead electrode and a semiconductor element can be inspected easily. A semiconductor device includes: a base portion; a semiconductor element mounted on the base portion; a metal part erect with respect to the semiconductor element and having one end bonded, with a bonding material, to a principal surface of the semiconductor element opposite to another principal surface of the semiconductor element mounted on the base portion; and a lead electrode connected to the semiconductor element through the metal part. The lead electrode includes a through hole extending in a thickness direction. The metal part connects the semiconductor element to the lead electrode, while inserted into the through hole of the lead electrode together with a part of the bonding material.

Abstract: Discussed is a display apparatus including a wiring board having wiring electrodes; a conductive adhesive layer covering the wiring electrodes; a plurality of semiconductor light emitting devices coupled to the conductive adhesive layer and electrically connected to the wiring electrodes; and an insulating material disposed between the plurality of adhesive regions to fill between the plurality of semiconductor light emitting devices, wherein each electrode of the plurality of semiconductor light emitting devices includes a first conductive electrode, a first conductive semiconductor layer on the first conductive electrode, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, and a second conductive electrode on the second conductive semiconductor layer, and wherein the second conductive electrode is disposed on one surface of the second conductive semiconductor layer.

Abstract: An integrated circuit package includes a support substrate having a front side and a back side and an optical integrated circuit die having a back side mounted to the front side of the support substrate and having a front side with an optical sensing circuit. A glass optical element die has a back side mounted to the front side of the optical integrated circuit die over the optical sensing circuit. The mounting of the glass optical element die is made by a layer of transparent adhesive which extends to the cover the optical sensing circuit and a portion of the front side of the optical integrated circuit die peripherally surrounding the optical sensing circuit. An encapsulation material body encapsulates the glass optical element die and the optical integrated circuit die.

Abstract: A semiconductor device includes: a die pad having a top surface; a semiconductor chip provided on the top surface; a first solder provided between the top surface and the semiconductor chip, the first solder bonding the top surface and the semiconductor chip; a first metal film provided on the semiconductor chip; a first insulating film provided on the first metal film and having a first opening; a connector having a first end and a second end, the first end being provided on the first metal film in the first opening; a second metal film provided in the first opening, the second metal film having a plurality of second openings provided so as to surround a portion of the first metal film in contact with the first end, and the second metal film being provided between the first end of the connector and the portion of the first metal film; a plurality of second insulating films provided in direct contact with the first metal film in each of the second openings; and a second solder provided between the second meta

Abstract: A method of manufacturing a flip chip package includes forming a plurality of semiconductor chips and bonding the semiconductor chips to a package substrate. The method further includes electrically testing the plurality of semiconductor chips on the package substrate, molding the tested semiconductor chips, and singulating the molded chips. Electrically testing the semiconductor chips includes covering the semiconductor chips with a protection member.

Abstract: A method of manufacturing an electronic device includes a preparation step of preparing a substrate to which a lead is bonded, and a molding step of mounting a cap in a mold in a state in which the cap is disposed on the substrate and forming a mold portion by filling a mold material into the mold. The mold includes a first mold including a cap mounting portion, and a second mold including a lead pressing portion. The molding step includes a step of mounting the cap in the cap mounting portion, a step of mounting the substrate on the cap, a step of pressing the lead with the lead pressing portion to elastically deform the lead, and biasing the substrate toward the cap by a restoring force generated in the lead, and a step of filling the mold material into the mold.

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ?100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.

Abstract: A power module including a main housing, a power element, and at least one assembling component is provided. The main housing has at least one side wall and at least two ribs extending from the side wall. The power element is disposed in the main housing and is closely pressed against a heat dissipation structure by the side wall. The assembling component includes a main section and two bending sections. The main section is located between the two ribs and includes a central portion, at least one movable component, and a peripheral portion. The central portion has a fastening portion, the peripheral portion surrounds the central portion, and the movable component is connected between the central portion and the peripheral portion. The two bending sections are respectively connected to two opposite sides of the peripheral portion and are respectively embedded in the two ribs.

Abstract: A package structure is provided. The package structure includes a substrate, a cover element, a semiconductor device, a protruding element, and an adhesive element. The cover element is disposed on the substrate and having a ring portion, a space is surrounded by the ring portion, and a recess is formed on a surface of the ring portion that faces the substrate. The semiconductor device is disposed on the substrate and disposed in the space surrounded by the ring portion, wherein the semiconductor device is spaced apart from the recess by the ring portion. The protruding element extends from the substrate and disposed in the recess. The adhesive element is disposed in the recess, wherein in a top view, the semiconductor device is surrounded by the protruding element.

Abstract: A power semiconductor module includes a substrate with a structured metallization layer and a number of semiconductor chips. Each chip has a first power electrode bonded to the metallization layer. A leadframe is laser-welded to second power electrodes of the semiconductor chips for electrically interconnecting the semiconductor chips. A control conductor is attached to the leadframe opposite to the semiconductor chips and is electrically isolated from the leadframe. The control conductor is electrically connected to control electrodes of the semiconductor chips in the group.

Abstract: A power semiconductor module comprises abase plate (1); a semiconductor chip (2) disposed on and in contact with a top surface of the base plate (1), a preform (3) disposed on and in contact with a top surface of the semiconductor chip (2); and a pressing element (4) in contact with and applying a pressure onto a top surface of the preform (3). The preform (3) comprises a first electrically conductive layer (6) and a second electrically conductive layer (5). The first electrically conductive layer (6) has at least one protrusion (7) protruding towards the top surface of the semiconductor chip (2) and defining a recess (9) in the first electrically conductive layer (6) of the preform (3), wherein the recess (9) may annularly surround the protrusion (7). The at least one protrusion (7) is made from the same material as the first electrically conducting layer (6) and integrally formed with it or the first electrically conducting layer (6) and the at least one protrusion (7) are made from different materials.

Abstract: Some embodiments relate to a semiconductor structure including a method for forming a semiconductor structure. The method includes forming a lower conductive structure within a first dielectric layer over a substrate. An upper dielectric structure is formed over the lower conductive structure. The upper dielectric structure comprises sidewalls defining an opening over the lower conductive structure. A first liner layer is selectively deposited along the sidewalls of the upper dielectric structure. A conductive body is formed within the opening and over the lower conductive structure. The conductive body has a bottom surface directly overlying a middle region of the lower conductive structure. The first layer is laterally offset from the middle region of the lower conductive structure by a non-zero distance.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a peak portion on the substrate, forming a gate insulating layer on the substrate and the peak portion, forming a gate bottom conductive layer on the gate insulating layer, and forming a first doped region in the substrate and adjacent to one end of the gate insulating layer.

Abstract: An organic light-emitting display apparatus includes a substrate; a pixel electrode over the substrate; a pixel-defining layer including an opening that exposes at least a portion of the pixel electrode; an intermediate layer, which is over the portion of the pixel electrode exposed by the opening and includes an organic emission layer; a counter electrode over the intermediate layer; and an encapsulating structure, which is over the counter electrode and includes at least one inorganic layer and at least one organic layer, and the at least one organic layer includes quantum dots and is in the opening.

Abstract: A method for forming a fin field effect transistor device structure includes forming a first fin structure in an input/output region of the substrate with a fin top layer and a hard mask layer over the first fin structure. The method also includes forming a dummy oxide layer across the first fin structure. The method also includes forming a dummy gate structure over the dummy oxide layer across the first fin structure. The method also includes forming spacers on opposite sides of the dummy gate structure. The method also includes removing the dummy gate structure over the first fin structure. The method also includes removing the dummy oxide layer and trimming the first fin structure. The method also includes forming a first oxide layer across the first fin structure. The method also includes forming a first gate structure over the first oxide layer across the first fin structure.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a photodetector region provided in a substrate. A dielectric material is disposed within a trench defined by one or more interior surfaces of the substrate. The trench has a depth that extends from an upper surface of the substrate to within the substrate. A doped silicon material is disposed within the trench and has a sidewall facing away from the doped silicon material. The sidewall contacts a sidewall of the dielectric material along an interface extending along the depth of the trench.

Abstract: A semiconductor package device includes a package substrate, an interposer on the package substrate, a semiconductor package on the interposer, and an under-fill between the interposer and the semiconductor package. The interposer includes at least one first trench at an upper portion of the interposer that extends in a first direction parallel to a top surface of the package substrate. The at least one first trench vertically overlaps an edge region of the semiconductor package. The under-fill fills at least a portion of the at least one trench.

Abstract: Implementations described herein are related to a semiconductor device package having an improved baseplate. In such an improved baseplate, there is a recess cut out of a region of a surface of the baseplate such that the recess has a first sidewall having a first thickness above a recess base and a second sidewall having a second thickness above the recess base. A substrate, e.g., a direct bonded copper (DBC) substrate, may be attached to the baseplate at a recess base using, e.g., a solder layer between the recess base and a surface of the substrate.

Abstract: A clip for connecting an electronic component with a carrier in a package is provided. The clip includes a clip body having a component connection portion configured to be connected with the electronic component to be mounted on the carrier, and a carrier connection portion configured to be connected with the carrier. The clip further includes at least one locking recess in a surface portion of the clip body, the surface portion being configured to face the carrier. The at least one locking recess is configured to accommodate material of an encapsulant of the package so as to lock the encapsulant and the clip. A corresponding method of manufacturing the package is also provided.