Abstract: A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an address stored in a temporary memory array. When the address does not match any address stored in the temporary memory array, a wait instruction is sent to a processor and the address is analyzed to determine which portion of compressed data stored in a map memory array to decompress. The map memory array stores data containing compressed addresses of defective cells in a first memory array. The portion of compressed data is then decompressed to provide expanded data when the address does not match any address stored in the temporary memory array. The expanded data are then written to the temporary memory array, and the expanded data are compared to the address to determine when the address corresponds to an expanded datum of the expanded data.

Abstract: A memory address generator in a convolutional interleaver/deinterleaver for correcting errors occurred in a data transmission of communication systems.

Abstract: A compressed data amount calculation section calculates the data amount of compression-coded data corresponding to input multimedia information in advance before a code image is recorded. A precode image data generation section generates precode image data determined on the basis of the calculated data amount and displays the precode image data on a display section. The user changes various coding parameters through a user setting section while observing the displayed precode image data to regenerate the precode image data, thereby obtaining the desired size. A code image data generation section generates actual code image data in accordance with the changed coding parameters.

Abstract: In an SDRAM, when a spare column selection line is not used, access to a column selection line is started at a first time at which complementary column address signals are defined, and access to the column selection line is stopped until a second time at which the level of a redundant column decoder activation signal is defined when the spare column selection line is used. Compared with the case in which access to the column selection line is always stopped until the second time, the access speed is increased.

Abstract: A method of testing a logic device that includes the steps of identifying a first test vector corresponding to a test failure resulting from testing of the logic device (10), converting the first test vector from an input pin format into state data associated with the logic device, and searching the internal state data to identify a set of last shift transitions. A method of making a logic device having a specification frequency, the method including the steps of providing an integrated circuit, testing the integrated circuit using a scan test pattern at a frequency at least as great as the specification frequency, performing a diagnosis procedure to produce a diagnosis result, and producing the integrated circuit in a final form after the diagnosis result indicates a non-functional problem. The diagnosis result indicates at least one of a non-functional problem and a speed problem.

Abstract: A request frame number indicative of a minimum frame number of data frames which have not been received and data frame reception confirmation information indicative of whether or not receptions of data frames from a frame number next to a minimum frame number in the data frames which have not been received to the last predetermined frame number have been confirmed are included in a feedback frame. Thus, there can be obtained a data communication method which makes it possible to reduce an unnecessary re-transmission to a reception side data communication apparatus carried out even when data frames transmitted from a transmission side data communication apparatus to the reception side data communication apparatus have been correctly received by the reception side data communication apparatus, and to hence improve a throughput of transmission of a data frame from the transmission side data communication apparatus to the reception side data communication apparatus.

Abstract: An external flexible bay system includes an external flexible bay, a modular battery pack and a modular disk drive. The external flexible bay is adapted to receive either the modular battery pack or the modular disk drive to facilitate use of such devices with a portable PC. The external flexible bay includes a parallel port which enables an external I/O device, such as a printer, to be connected thereto. The external flexible bay contains circuitry to automatically sense whether a printer is connected and to determine whether a modular battery pack or modular disk drive has been inserted therein. In order to ensure proper configuration, the external flexible bay includes a mode switch for selecting between a floppy mode and a printer mode.

Abstract: Computerized system and method are provided which have particular utility in the field of automated testing. In one embodiment of the method of the present invention, an array is stored in computer-readable memory. The array has a plurality of tuples, each of which includes a respective action field, a respective expected result field, a respective success field, and a respective failure field. The respective action field is for specifying at least one respective action whose performance by the system-under-test is to be commanded. The respective reaction field is for specifying at least one respective expected result to be achieved by performance of the respective action. The respective success and failures fields are for specifying further appropriate actions to be executed if the respective expected result is achieved (i.e., if a success condition occurs), or if the respective expected result is not achieved (i.e., if a failure condition occurs).

Abstract: An NLTS (non-linear transition shift) correction circuit for hard disk drives improves flexibility in modifying algorithm of the data pattern analysis utilized therein and NLTS correction precision thereof. The NLTS correction circuit of the present invention uses a data pattern analyzer including a CPU and a data pattern analysis program. Selector control signals produced by this analyzer are stored in a selector control signal buffer memory and are output to a selector in synchronization with the output from a data buffer memory. The pattern of data to be recorded can be analyzed while flexibly responding to the fluctuations in the characteristic of the recording medium by modifying the analyzing program. Moreover, the difference in the amount of delay between the delay lines can be calibrated by adding a circuit for calibrating the NLTS correction value, which includes a circuit that converts the duty cycle of the record data signal to voltage value.

Abstract: A time-varying trellis code is used to obtain a desired effective code rate which produces an encoder output directly mappable onto a signal constellation. The time-varying trellis code is obtained by using a variable rate encoder which produces, at its output, the correct number of bits to map directly onto the desired signal constellation. The input data stream is coded at a first code rate during a first selected time interval, and at a second code rate during a second selected time interval. By varying the code rate at periodic intervals, a third effective code rate is obtained.

Abstract: The objective of the invention is to offer a Reed-Solomon decoding device in which it is possible to perform decoding calculations at high speed without greatly increasing the circuit scale.

Abstract: A system with a ferroelectric memory has a low probability of soft error thereby decreasing the possibility of serious damage to the system that might result from soft errors. The ferroelectric memory is provided with an overwrite-inhibited memory block 122 for storing the OS (Operating System) and applications, and an overwrite-free memory block 123 which is a work area. The overwrite-inhibited memory block 122 includes a parity bit storage 125. A process for checking and correcting error performed about once a day. A command for starting the error checking and correcting procedures is triggered by a switch such as power source switch. When an error occurs in the ferroelectric memory 120, it is possible to recover the function of the system.

Abstract: A control device having control logics that respectively generate operated quantities by simutaneously parallel-processing observed quantities obtained from a controlled object. A switch selectively outputs one of the operated quantities to the controlled object based on instruction data.

Abstract: A method for classifying a device as being a first device type or a second device type, wherein the first and second device types are each contained a package which has a plurality of terminals. The method includes identifying at least one target terminal, testing the target terminal, and classifying the device based upon the testing act.

Abstract: The invention relates to an integrated circuit, comprising a number of independent clock domains. Seam circuits are provided in the interface signals paths between the clock domains in order to be able to isolate clock domains from each other during testing. Each seam circuit comprises a feedback loop having a multiplexer and a flip-flop feeding a first input of the multiplexer, a second input of the multiplexer being connected to the seam input, an output of the feedback loop being connected to the output; so that a first state of the multiplexer allows loading of a data bit in the feedback loop via the seam input, and a second state of the multiplexer freezes the data bit in the feedback loop.

Abstract: An error correcting decoding apparatus of an extended RS code capable of solving a problem of a conventional method in that Euclidean algorithm or Berlekamp-Massey algorithms must be performed twice in the worst case because of complicated algorithm, and this results in a delay of decoding. The present apparatus generates a syndrome from a received word, estimates the number of errors having occurred in the received word, computes error-locator polynomials and error-value polynomials while changing the initial values and ending condition of the Euclidean algorithm computation in accordance with the number of errors estimated, computes error locations and error values by performing Chien's search on these polynomials, and carries out the error correction on the basis of the error locations and error values. This makes it possible to achieve decoding by performing the Euclidean algorithm computation only once.

Abstract: An electronic apparatus includes a CPU, a ROM, a RAM, an input port, a data bus, an address bus, a patching portion address register and a patching interrupt vector register which are connected to the data bus. A comparator compares a coincidence of the address stored in the address register with an address on the address bus and, in response thereto, supplies an interrupt to an interrupt control portion of the CPU. The interrupt control portion of the CPU is also supplied with other interrupts, for other processing. Further, an external storage device, connected to the input port, supplies a program bug patching information to be stored into the RAM. The RAM includes a stack area in which, during interrupt processing, there are saved data written in the address register and the patching interrupt register. Thus, patching of program bugs can be carried out even during an interrupt.

Abstract: A flexible test environment for automatic test equipment, whereby sequences of steps for developing and executing test programs are specified using hierarchical trees of nodes. The nodes in one tree include end leaves that correspond with the test program development steps, and the nodes in another tree include end leaves that correspond with the test program execution steps. Further, the end leaves in both trees have a plurality of associated properties, which are used for specifying test program flow and for indicating methods to be called when the steps are executed. The test environment can be easily adapted to a distributed tester architecture.

Abstract: This invention describes a test tool based on a PC workstation. This test tool is used to validate any E1 framing telecommunication device. In order to comply with the CCITT G.706 recommendations, a device has to pass a series of test cases that are predetermined. Each test case contains test sequences according to the CCITT G.706 specifications. The purpose of this test tool is to generate a set of stimuli in the transmission mode, whereas in the reception mode, the value of the data returned by the tested device is analyzed and compared with the expected response. The data bytes are structured as for E1 multiframe format containing 16 frames of 32 timeslots, where each timeslot is a data byte. According to the G.706 recommendations, timeslot 0 is dedicated to the frame and multiframe alignment and to the CRC test.

Abstract: In a tester for testing circuits, apparatus and methods for acquiring waveform data from a circuit under test. While a test program is being run by the tester, waveform acquisition strobe events are generated for application to a terminal of a circuit under test. A measurement circuit receives the waveform acquisition strobe events and applies each strobe event to the terminal of the circuit and generates result signals representing the result of applying the strobe events to the terminal. A capture memory receives and stores result signals generated by the measurement circuit.