Abstract: A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line.

Abstract: An encoding/decoding system for RAID-6 or multiple track tape systems uses one of a selected set of values for m, with m+1 prime and the field GF(2.sup.m) generated by the irreducible polynomial:g(x)=x.sup.m +x.sup.m-1 + . . . +x.sup.2 +x+1.The system performs Galois Field multiplication operations as a combination of cyclic shifting and exclusive-OR operations, and determines multiplicative inverses of weight one, two and three (m+1)-bit symbols by raising various (m+1)-bit symbols to selected powers of two. Using this system, the value of m may be chosen to be as large as or larger than the sector or tape block, and the encoding and decoding is performed once per sector or block.

Abstract: A pattern generating apparatus used in quality judgment testing of memories incorporating a predetermined signal transfer configuration such as a protocol transfer system, the apparatus having: an address generating device for sequentially generating address patterns for specifying storage regions in a test memory; a first control device for converting the sequentially generated address patterns into a signal transfer configuration for the test memory and supplying these to the test memory to sequentially access the storage regions specified by the respective address patterns; and a second control device for determining a condition in which the test memory is operated with respect to the address pattern generated by the address generating device, and controlling a generation timing for the address pattern based on this.

Abstract: A system and method are disclosed for modulation encoding data for storage or transmission on a multilevel medium. The method includes encoding a first portion of data using a first tier modulation code. The first tier modulation code maps a first portion of the data onto a first set of symbols. A second portion of data is encoded using a second tier modulation code. The second tier modulation maps the second portion of the data onto a second set of symbols. The second tier modulation code has error correcting characteristics. A third set of symbols is determined based on the first set of symbols and the second set of symbols. The third set of symbols is suitable to determine nominal read signal levels from a multilevel medium. Improved error characteristics are realized for encoding data for storage or transmission on a multilevel medium.

Abstract: A memory controller and system for providing access to PCMCIA standard memory cards and non-standard memory cards. Non-standard memory cards are memory cards that are compliant with PCMCIA standards for sockets and are non-compliant in other respects. The memory controller has a register for storing a code that indicates whether a memory card is a PCMCIA card or a non-standard memory card. An access control circuit in the memory controller activates and deactivates memory card control signals at times required by the memory card and as indicated by the memory card type. An acknowledge control circuit generates an acknowledge signal to a requesting processor at a time prescribed by the type of memory card.

Abstract: The address data acquiring section causes the format information storage section to store the format information concerning the allocation of addresses to the blocks of a code to be read out and the plural addresses provisionally determining section restores the address data from each of two or more than two blocks found in a picked up image and detected by the block detecting section. Then, it causes the address determining section to determine the correct address of each of the blocks according to the provisionally determined address data for the two or more than two blocks and the format information stored in the format information storage section. The information data reproducing section rearranges and reproduces the block data restored from the blocks detected by the block detecting section and restored by the block data restoring section according to the address information determined by the address determining section.

Abstract: A method and apparatus for generating test data is presented. A data generator produces data using element specifications contained in an input script. The data generator includes a specification analyzer and data synthesizer. The data generator produces the data that includes varied combinations of the element specification generated in a particular order. Both the combination and the particular order in the generated sequence may vary in accordance with a specified method of data generation. Three methods of data generation--carry-out method, grey code method, and all-change method--are described.

Abstract: A detector system employing a Viterbi algorithm includes an apparatus and method which constructs a double-state trellis structure for determining a most likely received symbol sequence with respect to an observed sequence of channel output samples. In the double state trellis, pairs of states are identified having equivalent branch metric values which also have a same decision during a path select, thus allowing these pairs of states to share a compare operation of a previous state metric. Consequently, to calculate an updated or current state metric value, an add, compare and select (ACS) circuit may compare only the previous state metric values to determine a minimum value for a transition between two states while combining each previous state metric value with its corresponding branch metric to provide an updated or current state metric value.

Abstract: A method of encoding data is described herein. According to the method, source data elements are coded using one or more product codes having a common component code. The resulting one or more primary product codewords consist of a plurality of first codewords of the common component code. One or more first sets of codewords of the common component code are assembled such that each of the first sets comprises two or more distinct first codewords forming part of a same primary product codeword. Each of the codewords of each of the first sets is codeword-mapped to a second codeword of the common component code using a one-to-one codeword-mapping. One or more second sets of second codewords are provided, where each second set corresponds to a first set of codewords. The codeword-mapping includes re-ordering, according to a known interleaving pattern, the symbols within a codeword.

Abstract: A computationally simple yet powerful forward error correction code scheme for transmission of real-time media signals, such as digitized voice, video or audio, in a packet switched network such as the Internet. An encoder at the sending end derives p redundancy blocks from each group of a k payload blocks and concatenates the redundancy blocks, respectively, with payload blocks in the next group of k payload blocks. At the receiving end, a decoder may recover up to p missing packets in a group of k packets, provided with the p redundancy blocks carried by the next group of k packets. The invention thereby enables correction from the loss of multiple packets in a row, without significantly increasing the data rate or otherwise delaying transmission.

Abstract: A method and digital system for testing scannable memory and combinational networks. The scannable memory is configurable into several scan chains. Each chain may have a different effective clock rate, as determined by respective clock enable signals. The method and digital system allow scan testing of digital circuits that use a single operational clock rate and several functional clock enable signals to effect slower lock operating rates. The digital system includes memory elements having scan enable and clock enable inputs.

Abstract: The present invention relates to the error control method in inter-multi-user multimedia communication. There are error detection, error reporting and error recovery functions in the conventional error control method which finds out and solve the error occurring at the time of data transmission between transmitter and receiver, however, these functions are an error control method occurring in end-to-end communication consisting of one transmitter and one receiver and are not appropriate to solving errors occurring concurrently and in a bundle between one or some transmitters and many receivers in many-to-many multiple points inter-multi-user communication such as multimedia communication. Therefore, the present invention uses the damping technique to minimize the number of error control packets of which all the receiver having sensed the error concurrently request the resend based on the NACK.

Abstract: The present invention, generally speaking, provides an integrated circuit testing technique in which hardware accessibility of selected components is exploited in order to avoid scan insertion overhead but achieve as good or better fault coverage than if scan insertion had been used. The term "pseudo-scan" is used to refer to the use of read and write instructions to achieve the equivalent effect as scan insertion without the addition of scan flops. Existing ATPG tools may be used without modification by performing scan insertion on a "dummy" circuit and performing ATPG on the scan-augmented dummy circuit. The resulting ATPG vectors are then modified to perform pseudo scan of selected components of the original circuit.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: The invention relates to an arithmetic unit (AU) in combination with an algebraic block ECC decoder for controlling errors in an electronically recorded digital data message by performing at least one of a plurality of predetermined arithmetic operations on the data message in one or more of a plurality of subfields of a first GF(2.sup.12) or a second GF(2.sup.8) finite field. The arithmetic operations are selected either from a first group of operations associated with a first subfield GF(2.sup.4) as cubically extended to the first finite field GF(2.sup.12) or as quadratically extended to the second finite field GF(2.sup.8), or selected from a second group of operations associated with a second subfield GF(2.sup.6) as quadratically extended to the first finite field GF(2.sup.12).

Abstract: The bits of a data block are logically partitioned into an array that includes a number of columns equal to a number of memory devices and a number of rows equal to a number of bits of the data block stored in each memory device. Each memory device contributes one bit to each row. In one embodiment, the bits from a memory device are stored in the same column position of all the rows. One check bit is associated with each row. The check bit is computed by taking the parity of the row associated with the check bit and zero or one column. Each column is assigned to at least four check bits. If a check bit has a column assigned to it, then the check bit is generated by computing the parity of the associated row and the column assigned to the check bit. Alternatively, if the check bit does not have a column assigned to it, the check bit is generated by computing the parity of the row assigned to the check bit only. Each column is assigned to at least four check bits and is assigned to an even number of check bits.

Abstract: A method and system in a data processing system are disclosed for the retransmission of only a portion of a data packet which had originally been transmitted incorrectly. A first data link is established between a first computer system and a second computer system. In response to the establishment of the first data link, a second data link is established between the first and second computer systems, whereby the first and second data links are related. A plurality of data packets are transmitted from the first computer system to the second computer system utilizing the first data link. Each of the data packets includes a plurality of segments. A determination is made whether each of the plurality of data packets is received correctly. In response to a determination that one of the plurality of data packets is received incorrectly, a portion of the data packet which was transmitted incorrectly is determined.

Abstract: The present invention provides systems and methods for controlling associated processes of a process facility and, in particular, for distributing data among various nodes of a real time process control system that controls such a facility. An exemplary process control system includes a plurality of sensors, controllable devices, and communication paths, as well as a computer system. The sensors and controllable devices are associated with various ones of the processes of the process facility, and the communication paths associate the sensors and controllable devices with the computer system. The computer system operates on data relating to the process facility, and distributes the data among the nodes thereof. The nodes are associated by the communication paths, and the computer system further includes notification controllers.

Abstract: When the number of pieces of error position information detected by using one symbol, of internal and external symbols constituting an error correcting code added to information data, which has a data sequence substantially corresponding to the reception order of the information data exceeds the erasure correcting ability based on the other symbol, error position information is selected upon weighting based on the continuity of the error position information in consideration of the fact that burst error position information exhibits high continuity. By selecting error position information upon weighting based on continuity, erasure correction, which cannot be performed in the prior art, can be performed.

Abstract: This invention relates to a circuit for calculating a syndrome on packets of n p-bit data, including a syndrome `register receiving the sum of each received datum and of the contents of the syndrome register modified by a first interconnection matrix corresponding to the p-th power of a generator polynomial. Each received datum defines a new packet of n data and the above-mentioned sum includes the datum preceding the new packet, modified by a second interconnection matrix corresponding to the n-th power of the first matrix.