Abstract: A serial to parallel interface for coupling multiple channels of audio input data to a digital audio workstation (DAW) having at least one processor capable of performing digital signal processing functions is formed from a programmable ASIC. The serial to parallel interface includes configuration registers which may be programmed to allow the interface to communicate with external audio devices that are operating in any audio format and bit width format. The serial to parallel interface includes a double buffered input and output serial datapath. The double buffered input and output datapath eases timing constraints between the interface and the DSP, thus allowing the DSP the flexibility of being able to read data at almost any point during an audio data transmission period. In addition, the double buffering mechanism within the serial to parallel interface allows for sample receipt errors to be isolated from the DSP, thereby ensuring the integrity of the audio data before it is propagated to the DAW.

Abstract: A computer system that implements communication support with a minimum amount of main memory. The computer system provides a Basic Input/Output System (BIOS) for execution in Random Access Memory (RAM). Included in the BIOS is the communication initialization and runtime code. Upon initialization, the communication initialization code is executed, configuring and initializing communication devices, including a Universal Serial Bus (USB) device. After the initialization, the runtime communication code is moved to a secure memory, such as System Management Mode (SMM) memory. The runtime communication code is executed in response to an interrupt to the secure memory. If the secure memory is SMM memory, then a SMI will trigger the execution of the communication code. The main memory is not accessed to execute the runtime communication code.

Abstract: A transceiver device having a forward error correction decoder providing at least one forward error correction metric and a data integrity monitor providing at least one automatic retry query metric to a data processor or CPU. The data processor or CPU is responsive to the forward error correction metric and the automatic retry query metric and has outputs providing a forward error correction value and an automatic retry query value to the forward error correction/data encoder and decoder.

Abstract: A method of forming quantum error-correcting codes by first forming a stabilizer for a Hilbert space. A quantum information processing device can be formed to implement such quantum codes.

Abstract: A data recording method error-correction-code (ECC)-encodes and modulates data of a file to be recorded in units of data blocks, and records the encoded and modulated data on a digital versatile disk-random access memory (DVD-RAM). Dummy data is added to make a last data block when the size of a file to be recorded is not an integer multiple of a data block, and then the last data block is ECC-encoded and modulated for recording the same on a DVD-RAM. The recording of data is performed in a recording region of a DVD-RAM where no data is recorded, and also starts from a recording region just next to the last data even when the last data of the previously recorded file includes dummy data.

Abstract: A system and method for identifying long paths in an integrated circuit are described. An integrated circuit chip is subjected to input test signals of progressively shorter cycle time until the chip fails to produce a correct output. The cycle time of the signal resulting in the failure of the chip is defined as T. A signal having cycle time T'=T+.DELTA.T is then applied to the integrated circuit, where the signal of cycle time T' is known to result in proper operation of the chip. The chip is then observed for switching activity during the period .DELTA.T which occurs beginning at a time T measured from the beginning of the second signal of duration T' until the end of the signal of duration T'. The location of the switching activity is used to identify the path or paths of the circuit that resulted in failure of the chip. In a preferred embodiment of the invention, the switching activity is detected using an optical measurement system capable of detecting light generated by transistor switching activity.

Abstract: A syndrome calculation unit 101 forming a first pipeline stage, a Euclidean algorithm arithmetic operation/error value calculation unit 102 and a Chien search unit 103 together forming a second pipeline stage, and an error correction unit 105 forming a third pipeline stage are provided. The unit 102 implements, by iterative use of a single inverse element calculator, a single Galois multiplier, and a single Galois adder, the Euclidean algorithm arithmetic operation of finding an error locator polynomial .sigma.(z) and an error evaluator polynomial .omega.(z) from a syndrome polynomial S(z) and the calculation of finding an error value e.sub.u by dividing an error evaluation value .omega.(.alpha..sup.-ju) by an error locator polynomial differential value .sigma.'(.alpha..sup.-ju).

Abstract: Multiplex transmission apparatus 10 on the transmitting side multiplexes received signals from non-voice signal input output apparatus 14 and voice signal input output apparatus 16, and also transmits the multiplexed signal from communications network 30 by digital portable telephone 12 on the transmitting side. The digital portable telephone transmits a signal per 20 msec, so that multiplex transmission apparatus 10 alternately transmits the voice signal and the non-voice signal at an interval of 20 msec, for example. Multiplex transmission apparatus 20 sorts out the voice signal and the non-voice signal from the supplied signal by checking the error detecting code of the supplied signal. Multiplex transmission apparatus 20 can judge the type of the signal according to the type of the error detecting code, because a different error detecting code is added to each signal.

Abstract: System and method for verifying the integrity of contents within a computer file. A security value S is stored within the file. A verification function f is applied against the entire contents of the file including S, where f is a function of S. Results R of the applying step are compared against a preselected value r, where r is not stored within the file. When R equals r, a determination is made that the file has not been modified. f is typically a distributive invertible function such as the Cyclic Redundancy Check (CRC) function known as modulo p, where p is a prime number and is one bit greater than the length of S. Typically, the value of r is zero. Before executing the verification function f, a check generating program is first executed. This check generating program is executed by a computer that is remote from the file, further enhancing the security of the system.

Abstract: A data packet is transmitted by dividing it into sub-packets, for example by distributing successive bytes of the data packet to different sub-packets each containing at most p.sup.n -1 symbols, where p is a prime number, and transmitting the sub-packets along two or more respective paths. CRC checksums are added to the sub-packets, the checksum for each path being generated using a different and respective generator polynomial of degree b. These generator polynomials are selected so that, for arithmetic carried out modulo p, each polynomial has a respective factor of degree at least b-n+1, and the collection of polynomials which are each exactly divisible by all such factors constitutes a BCH code. As a result the system has advantageous properties in respect of error detection and implementation.

Abstract: A method and apparatus for improving reliability of a descrambling operation of data in a DVD player. The method includes the steps of establishing a bit value corresponding to a predetermined portion of ID data in each of sectors of the data to be descrambled as an initial value for descrambling the data including ID data, the bit value being used during the descrambling of the data; checking an error of the ID data on a basis of the bit value; correcting the error of the ID data if the error is generated in the ID data; and descrambling the data by sector units. As a result, it is possible for a specific bit value to be maintained uniformly in one basic data block and for the specific bit value to have a continuity between basic data blocks, thereby minimizing an erroneous operation due to an error generated in the ID data during the descrambling of the data.

Abstract: A communications unit configured to be implemented in an ASIC environment utilizes only a small amount of chip surface area and requires a minimum number of pins. The unit operates asynchronously with respect to the ASIC internal clock so that communications can occur independent of such internal clock. In one embodiment the communications unit includes a controller coupled to a shift register via a data bus. Pin connections to the controller include a request line REQ, an input/output control line I/O (or INOUT), an acknowledgement line ACK, an external clock line EXTCLK, and a data line DATA. The shift register also is coupled, via a data bus, to a memory module, e.g., a RAM. An ASIC processor is coupled to the controller, shift register and memory module via control lines.

Abstract: A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a burn-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication.

Abstract: A memory device is described which includes a latch circuit for latching a normally externally provided signal during a test mode. The input pin which is normally enabled to receive the external signal is re-routed to provide an external reference voltage, Vref, to internal circuitry. During testing operations the external Vref signal is used. Once an integrated circuit is determined to be good, an internal generator circuit is set to provide Vref. The integrated circuit can be a flash memory device, and the input pin can be a BYTE command pin. This method of substituting the source of Vref eliminates time required to set the internal generator circuit in defective memory devices.

Abstract: A method for precisely locating and correcting data errors on a magnetic storage disk with a recording head, e.g. an MR head, in the presence of thermal asperities, scratches, or other data signal degradation causes is set forth. The method includes the steps of reading a sector of data and collecting ECC syndromes. At the same time, data errors may be detected and their proximate location determined, whereupon an ECC process is applied for correction of the errors. In the event the detected data errors are not correctable by the ECC, the method repetitively redefines the detected data error location and applies Forney's ECC erasure correction algorithm to each repetition. These repetitions are carried out a predetermined number of times until the data is corrected or the correction attempts are exhausted.

Abstract: An architecture for the isochronous transfer of information within a computer system in which a first isochronous stream of information is transferred, and asynchronous information is transferred independently from the transfer of the first stream. A translation is performed between the first stream and a second isochronous stream of information, and the second stream transfers information at a rate substantially the same as the rate at which the first stream transfers information. The second stream and the asynchronous information are concurrently transferred. In another embodiment of the present invention, a first isochronous stream of information is transferred, and the first stream is divided into a plurality of first service periods. Each first service period has a first duration and contains a first amount of information. A second isochronous stream of information is transferred independently from the transfer of the first stream.

Abstract: A method for setting test modes in a semiconductor ship and a device suitable for the method are provided. In the method, a power voltage is externally applied to the semiconductor chip. A predetermined signal is applied to an arbitrary selected external pin of the semiconductor chip. A first-state signal is applied to the test pin and a second-state signal is applied to the test pin a predetermined time later. The signal applied to the external pin is latched by the first-state signal applied to the test pin. The second-state signal applied to the test pin, a predetermined signal output when the first-state signal applied to the test pin is shifted to the second-state signal, and the latched signal are logically combined and the combined signal is output.

Abstract: In decoding an received codeword encoded for error correction purposes, a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step is presented whereby the polynomials are generated through a number of intermediate steps that can be implemented with minimal amount of hardware circuitry. The number of intermediate steps requires a corresponding number of cycles to complete the calculation of the polynomials. Depending on the selected (N, K) code, the number of cycles required for the calculation of the polynomials would be within the time required for the calculation of up-stream data. More specifically, an efficient scheduling of a small number of finite-field multipliers (FFM's) without the need of finite-field inverters (FFI's) is disclosed. Using these new methods, an area-efficient architecture that uses only three FFM's and no FFI's is presented to implement a method derived from the inversionless Berlekamp-Massey algorithm.

Abstract: The present invention relates to an error correcting and detecting apparatus that executes a decode process at high speed. The error correcting and detecting apparatus receives digital data including an error correction code and an error detection code and performs error correction and error detection on the digital data.

Abstract: A circuit for generating a pulse including a scan register having a first scan bit; first logic device receiving a first signal and generating a second signal; and a programmable delay circuit coupled to the scan register and the first logic device. The programmable delay circuit receives the second signal and generates a delayed second signal after a programmable period of time. The programmable period of time is determined by the first scan bit. The circuit also includes a logic circuit that recevies the second signal and the delayed second signal. The logic circuiit outputs the pulse having a pulse width proportional to the programmable period of time.