Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.

Abstract: For power management in a disaggregated computing system, a set of initial electrical power levels are allocated to a set of processor cores according to a predicted desired workload, where the set of initial power levels aggregate to an initial collective contracted power level. Electrical power is dynamically allocated to respective processor cores within the set of processor cores to produce a capacity to execute a collective demanded workload while maintaining the electrical power to the set of processor cores to an approximately constant electrical power level within a threshold of the initial collective contracted electrical power level.

Abstract: A method for migrating a power shelf between being supplied single-phase power and three-phase power includes coupling a second power adapter to an input of a power shelf of a rack while power is being supplied to the power shelf via a first power adapter coupled to another input of the power shelf. The first power adapter includes a multi-pin connector coupled to the input and three other connectors each coupled to respective single-phase power sources and the second power adapter includes a multi-pin connector configured to couple with the other input and another connector configured to couple with a three-phase power source.

Abstract: A method of rebooting a computing system in which a virtual machine (VM) runs on top of a hypervisor and a host operating system (OS) includes the following steps. Those steps are sending, from the host OS to the hypervisor, a pre-reboot notification that the host OS is going to reboot, in response to reception of the pre-reboot notification, saving by the hypervisor state of a session that is executing in the VM, rebooting the host OS, after the host OS is rebooted, logging on to the host OS using a credential provider that was previously registered with the host OS and sending a post-reboot notification from the host OS to the hypervisor, and in response to reception of the post-reboot notification, instantiating by the hypervisor a VM in which the session is resumed using the saved state of the session.

Abstract: Examples herein disclose monitoring an expected functionality upon execution of a system management mode (SMM) BIOS code. The examples detect whether a change has occurred to the SMM BIOS code based on the monitoring of the expected functionality. The change indicates that the SMM BIOS code is compromised.

Abstract: A method of initializing a secondary processor pursuant to a soft reboot of system software comprises storing code to be executed by the secondary processor in memory, building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space, fetching a first instruction of the code based on a first virtual address in the first address space and the first page tables, and executing the code beginning with the first instruction to switch from the first to the second page tables. The method further comprises, fetching a next instruction of the code using a second virtual address, which is identically mapped to a corresponding machine address, turning off a memory management unit of the secondary processor, and executing a waiting loop until a predetermined location in the physical memory changes in value.

Abstract: A background process is configured to periodically scrub a boot storage of a storage controller to ensure operational correctness of the boot storage. One or more foreground processes store a system configuration data of the storage controller in the boot storage of the storage controller. The background process and the one or more foreground processes are executed to meet predetermined performance requirements for the background process and the one or more foreground processes.

Abstract: Methods and apparatuses related to guardband recovery using in situ characterization are disclosed. In one example, a system includes a target circuit, a voltage regulator to provide a variable voltage to, a phase-locked loop (PLL) to provide a variable clock to, and a temperature sensor to sense a temperature of the target circuit, and a control circuit, wherein the control circuit is to set up a characterization environment by setting a temperature, voltage, clock frequency, and workload of the target circuit, execute a plurality of tests on the target circuit, when the target circuit passes the plurality of tests, adjust the variable voltage to increase a likelihood of the target circuit failing the plurality of tests and repeat the plurality of tests, and when the target circuit fails the plurality of tests, adjust the variable voltage to decrease a likelihood of the target circuit failing the plurality of tests.

Abstract: An embodiment of a memory apparatus may include a system memory, and a memory manager communicatively coupled to the system memory to determine a first amount of system memory needed for a boot process, initialize the first amount of system memory, start the boot process, and initialize additional system memory in parallel with the boot process. Other embodiments are disclosed and claimed.

Abstract: Systems and methods are provided to selectively provide power to a power supply line in a connector port. A power setting may be received, at a controller in an electronic device, for the connector port. The power setting may be set or changed by a processor in the electronic device. The power setting may be stored in a non-volatile storage. The controller may determine the power setting by reading the non-volatile storage. The controller may then apply the power setting to a switch using at least one control signal. The control signal selectively opens and closes the switch to respectively connect and disconnect a source of DC power to the power supply line in the connector port.

Abstract: An FPGA-based interface signal remapping method, relates to the technical field of nuclear power system, and solves the technical problems of poor reliability, readability and debuggability in the prior art. The method comprises dividing an internal programmable logic of an FPGA chip into two independent modules, with one module being an I/O module and the other module being a Core module, using the I/O module to process signal excursion occurring when an external signal is input to or output from the FPGA chip, signal collision caused by line multiplexing, metastable state in a data transmission process, and a data transmission error between asynchronous clock domains, using the Core module to implement logical processing and computing; and introducing a master clock signal outside the FPGA chip into the FPGA chip through a global clock pin of the FPGA chip. The method provided in the invention is suitable for a nuclear power protection system platform.

Abstract: A computing system includes a system board having a system controller device with an interrupt input. A system expansion bus connector is located on the system board and includes power pin(s) and an interrupt signal pin connected to the interrupt input. A peripheral device expansion card system is coupled to the computing system through system expansion bus connector and includes a system power reporting device coupled to the power pin(s) to receive power from the computing system via the power pin(s), and a card controller device coupled to the system power reporting device and to the interrupt signal pin. The card controller device determines, using the system power reporting device, a power state of the computing system. The card controller device also sends, to the system controller device through the interrupt signal pin, an interrupt signal that the system controller device interprets as a hot plug event.

Abstract: A semiconductor integrated circuit capable of efficiently suppressing power consumption when a power supply voltage is lowered is provided.

Abstract: The invention relates to an electronic mobile device (10; 20) comprising a device mode control unit (5) arranged to switch the mobile device from a first operational mode into a second operational mode. An orientation sensor (18; 28) is configured to measure a current orientation of the mobile device. A processor (6) periodically receives the current orientation from the orientation sensor, periodically stores the received current orientation as a reference orientation, and periodically calculates a differential angle between the current orientation and the stored reference orientation. The device is switched from the first operational mode to the second operational mode if the differential angle is above a predefined angular threshold value.

Abstract: Various embodiments provide methods, devices, and non-transitory processor-readable storage media enabling joint goals, such as joint power and performance goals, to be realized on a per heterogeneous processing device basis for heterogeneous parallel computing constructs. Various embodiments may enable assignments of power states for heterogeneous processing devices on a per heterogeneous processing device basis to satisfy an overall goal on the heterogeneous processing construct. Various embodiments may enable dynamic adjustment of power states for heterogeneous processing devices on a per heterogeneous processing device basis.

Abstract: Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.

Abstract: Methods and apparatus are described for detecting both single event latch-up (SEL) and electrical overvoltage stress (EOS) using a single, reconfigurable detection circuit. One example circuit capable of detecting a latch-up state and an overvoltage condition generally includes an impedance element coupled to a power supply node; a voltage divider coupled to the power supply node; a multiplexer having a first input coupled to a tap of the voltage divider, a second input coupled to a first portion of the impedance element, and a third input coupled to a second portion of the impedance element; a reference generator; and an analog-to-digital converter (ADC) having a first input coupled to an output of the multiplexer and a second input coupled to an output of the reference generator.

Abstract: Disclosed is an apparatus for an application including a core device for the application. The apparatus includes a power (preferably RF energy) harvester connected to the core device to power the core device. Also disclosed is a method for an application. The method includes the steps of converting RF energy into usable energy. There is the step of powering the core device with the usable energy.

Abstract: According to one example for verifying firmware module execution privilege, a firmware is booted on a processor. At least one firmware module in the firmware marked as a test module is identified, and verification with a production public key of metadata associated with the firmware is attempted. In an example, in the event that the metadata verifies successfully with the production public key, the firmware boot is halted when the processor determines that access to a video interface is available, and a user is alerted that a test module has attempted execution in a production firmware.

Abstract: Techniques for recovering virtual machine state and boot information used to boot an installed guest operating system on systems where the information has either been lost or is not present are described.