Abstract: A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.

Abstract: A semiconductor photomultiplier includes a microcell, a photosensitive diode, and an anti-reflective coating. The microcell has an insulating layer formed over an active region. The photosensitive diode is formed in the active region beneath the insulating layer. The anti-reflective coating is provided on the insulating layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Abstract: Integrated circuits with embedded memory structures, and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming first and second conductive interconnects over a semiconductor substrate. The method includes depositing a conductive material over the first conductive interconnect. Also, the method includes forming a memory structure over the conductive material, wherein the memory structure has an uppermost surface distanced from the first conductive interconnect by a first height. Further, the method includes forming an interlayer dielectric over the memory structure and forming a conductive via coupled to the second conductive interconnect, wherein the conductive via has a second height over the second conductive interconnect less than the first height. The method also includes forming first and second contact plugs through the interlayer dielectric.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer; an insulating layer; a first region disposed between the nitride semiconductor layer and the insulating layer and containing at least one element of hydrogen and deuterium; and a second region disposed in the nitride semiconductor layer, adjacent to the first region, and containing fluorine.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.

Abstract: A light emitting device having first, second and third dimensions that are orthogonal may include a light emitting semiconductor device configured to emit light via a first surface in a plane formed by the first and second dimensions. The light emitting device may further include a wavelength converting structure disposed on the first surface of the light emitting semiconductor device, the wavelength converting structure extending beyond the light emitting semiconductor device in the first dimension and the light emitting semiconductor device extending beyond the wavelength converting structure in the second dimension. The light emitting device may further include one or more optical extraction features in at least one gap formed by the wavelength converting structure extending beyond the light emitting semiconductor structure in the first dimension and/or formed by the light emitting semiconductor structure extending beyond the wavelength converting structure in the second dimension.

Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

Abstract: Light emitting devices (LEDs) and methods of manufacturing LEDs are described. A method includes providing a layer of a wavelength converting material on a temporary tape. The wavelength converting material includes at least a binder or matrix material, particles of a non-luminescent material, and phosphor particles and has a concentration of 60%-90% by volume particles of the non-luminescent material and phosphor particles. The layer of the wavelength converting material is separated on the temporary tape to form multiple wavelength converting structures, which are provided on an array type frame. Heat and pressure are applied to the wavelength converting structures on the array type frame.

Abstract: A high-frequency module includes a mounting substrate, electronic components, a sealing resin, and land conductors. The mounting substrate includes a front surface, a rear surface, and a side surface. The land conductors are provided on the rear surface. The electronic components are mounted on the front surface of the mounting substrate. A distance between the mounting surface of the land conductor near the side surface and the rear surface of the mounting substrate is larger than a distance between the mounting surface of the land conductor closer to the center than the land conductor near the side surface and the rear surface of the mounting substrate.

Abstract: A shielding element comprises a rigid substrate and at least one electrically conductive two-dimensional structure which is placed on one of the faces of the substrate. The substrate and the electrically conductive two-dimensional structure are such that the shielding element has optical-transmission and shielding-efficiency values at least one of which varies between two zones of the shielding element. Such a shielding element enables easier assembly of a detection system comprising multiple optical sensors.

Abstract: A processing temperature TS by a rapid thermal processing furnace is 1250° C. or more and 1350° C. or less, and a cooling rate Rd from the processing temperature is in a range of 20° C./s or more and 150° C./s or less, and thermal processing is performed by adjusting the processing temperature TS and the cooling rate Rd within a range between the upper limit P=0.00207TS·Rd?2.52Rd+13.3 (Formula (A)) and the lower limit P=0.000548TS·Rd?0.605Rd?0.511 (Formula (B)) of an oxygen partial pressure P in a thermal processing atmosphere.

Abstract: Apparatus and methods to control the phase of power sources for plasma process regions in a batch process chamber. A master exciter controls the phase of the power sources during the process sequence based on feedback from the match circuits of the respective plasma sources.

Abstract: A light-emitting device includes a plurality of light-emitting elements, a plurality of light-transmissive members, and a covering member. The light-emitting elements each has a light-extracting surface. The light-emitting elements each includes a layered structure including a semiconductor layer, and a plurality of electrodes connected to the layered structure. The light-transmissive members each has a lower surface facing the light-extracting surface of at least one of the light-emitting elements, and an upper surface opposite to the lower surface and having an area smaller than an area of the lower surface. The upper surface of each of the light transmissive members collectively constitutes a light-emitting part having an outermost periphery with a square shape or a circular shape. The covering member integrally covers lateral surfaces of the light-emitting elements and lateral surfaces of the light-transmissive members.

Abstract: A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.

Abstract: A method for fabricating a throughput-scalable sensing system is disclosed. The method includes receiving a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a semiconductor substrate and a plurality of sensors disposed in the semiconductor substrate. Each sensor of the plurality of sensors is disposed in a separate semiconductor die of the first semiconductor wafer. The method further includes bonding the first semiconductor wafer to the second semiconductor wafer and preparing the bonded first semiconductor wafer and the second semiconductor wafer for conductive path redistribution. The method further includes forming one or more redistribution paths and dicing an array of semiconductor dies as a group from the plurality of semiconductor dies. The array of semiconductor dies includes a group of sensors associated with the throughput-scalable sensing system.

Abstract: A method making it possible to obtain, on an upper surface of a crystalline substrate, a semipolar layer of nitride material comprising any one from among gallium, aluminium or indium, the method comprises the following steps: obtaining, on the upper surface of the crystalline substrate, a plurality of parallel grooves which extend in a first direction, one of the two opposite facets exhibiting a crystal orientation; etching a plurality of parallel slices which extend in a second direction that has undergone a rotation with respect to the first direction of the grooves in such a way as to obtain individual facets exhibiting a crystal orientation; epitaxial growth of the material from the individual facets.

Abstract: A patch on interposer (PoINT) package is described with a wireless communications interface. Some examples include an interposer, a main patch attached to the interposer, a main integrated circuit die attached to the patch, a second patch attached to the interposer, and a millimeter wave radio die attached to the second patch and coupled to the main integrated circuit die through the interposer to communicate data between the main die and an external component.

Abstract: A film deposition apparatus includes a process chamber and a turntable provided in the process chamber. The turntable includes a substrate receiving region to receive a substrate thereon and provided along a circumferential direction of the turntable. A source gas supply unit extending along a radial direction of the turntable is provided above the turntable with a first distance from the turntable such that the source gas supply unit covers an entire length of the substrate receiving region in the radial direction. An axial-side supplementary gas supply unit is provided in the vicinity of the source gas supply unit and above the turntable with a second distance from the turntable. The second distance is longer than the first distance. The axial-side supplementary gas supply unit covers a predetermined region of the substrate receiving region on the axial side in the radial direction of the turntable.