Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: A semiconductor device includes a semiconductor chip body having a surface on which a chip pad is disposed, a passivation layer covering the surface of the semiconductor chip body and providing a tapered hole revealing the chip pad, and a redistributed layer (RDL) structure disposed on the passivation layer. The RDL structure includes a first RDL interconnection portion spaced apart from the tapered hole and passing by the tapered hole and a second RDL overlapping pad portion configured to have a bottom portion contacting the revealed chip pad and configured to have a first side surface facing a side surface of the first RDL interconnection portion. A central portion of the first side surface of the second RDL overlapping pad portion extends toward the side surface of the first RDL interconnection portion such that the first side surface is curved.

Abstract: An organic light emitting diode display includes a plurality of pixels. At least one pixel is connected to a scan line receive a scan signal, a data line to receive a data signal, and voltage line to receive a driving voltage. The at least one pixel includes a switching transistor including a switching drain electrode to output the data voltage, a driving transistor including a driving source electrode connected to the switching drain electrode, and an organic light emitting diode connected to a driving drain electrode of the driving transistor. The driving source electrode is separated from the data line.

Abstract: A non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

Abstract: A structure of memory device is provided. The structure of memory device includes a first gate structure, disposed on a substrate, wherein the first gate structure is for storing charges. In addition, a second gate structure is disposed on the substrate. An insulating layer is in contact between the first gate structure and the second gate structure. An isolation structure integrated with the insulating layer is between the first gate structure and the second gate structure and at a top portion of the first gate structure and the second gate structure. The isolation structure provides an isolation distance between the first gate structure and the second gate structure.

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

Abstract: A semiconductor package includes a lower substrate, a connection substrate coupled to the lower substrate, the connection substrate having a lateral portion surrounding a cavity, and a first conductive pattern on a top surface of the lateral portion, a lower semiconductor chip on the lower substrate, the lower semiconductor chip being in the cavity of the connection substrate, and the lower semiconductor chip including a second conductive pattern on a top surface of the lower semiconductor chip, a bonding member connecting the first conductive pattern and the second conductive pattern to each other, and a top package on the first conductive pattern and the second conductive pattern.

Abstract: A semiconductor storage device includes a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a barrier metal layer provided on the insulating layer; an aluminum compound layer provided on the barrier metal layer; an amorphous layer provided on the aluminum compound layer and including a material that vaporizes upon its chemical reaction with fluorine; and a metal layer provided on the amorphous layer.

Abstract: A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

Abstract: A light emitting device includes a stacked structure and a first insulating layer covering at least side surfaces of the stacked structure including a p-type and n-type semiconductor layers, a light emitting layer sandwiched between the p-type and n-type semiconductor layers, an n-type electrode on the n-type semiconductor layer, an n-type contact layer sandwiched between the n-type semiconductor layer and the n-type electrode, a p-type electrode on the p-type semiconductor layer, an n-type contact pad on the n-type electrode, a p-type contact pad on the p-type electrode, and a semiconductor reflector between the light emitting layer and the n-type contact layer including multiple periods, each period including at least a first layer and at least a second layer having a refractive index different from a refractive index of the first layer. The light emitting device could be applied to wide color gamut (WCG) backlight modules or ultra-thin backlight modules.

Abstract: Novel thermoplastic polyhydroxyether-based compositions for use as a laser-releasable composition for temporary bonding and laser debonding processes are provided. The inventive compositions can be debonded using various UV lasers, leaving behind little to no debris. The layers formed from these compositions possess good thermal stabilities and are soluble in commonly-used organic solvents (e.g., cyclopentanone). The compositions can also be used as build-up layers for RDL formation.

Abstract: A display device includes a display element configured to generate a first color light, an encapsulation member on the display element and including an inorganic layer at an outermost portion thereof, a color conversion layer on the encapsulation member and including a first color conversion part configured to transmit the first color light, a second color conversion part configured to convert the first color light into a second color light, and a third color conversion part configured to convert the first color light into a third color light, and a buffer layer between the encapsulation member and the color conversion layer, wherein a difference in refractive index between the buffer layer and the inorganic layer is about 0.5 or less.

Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

Abstract: A semiconductor device includes a package substrate, a semiconductor chip on a first region of the package substrate, and a solder bump on a second region of the package substrate. The solder bump includes a core portion and a peripheral portion encapsulating the core portion. The peripheral portion includes a first segment with a first melting point and a second segment with a second melting point that is less than the first melting point.

Abstract: An image sensor image sensor may include: a substrate; photo-sensing elements formed in the substrate, each photo-sensing element responsive to light to produce a photo-sensing electrical signal; an antireflection layer formed over of the photo-sensing elements and structured to reduce optical reflection to facilitate optical transmission of incident light to the photo-sensing elements through the antireflection layer; color filters formed over the antireflection layer and arranged to spatially correspond to the photo-sensing elements, respectively, each color filter structured to select a designated color in the incident light to transmit through to a corresponding photo-sensing element; and partition patterns formed over the antireflection layer and arranged to spatially correspond to the photo-sensing elements, respectively, to partition light receiving area above the photo-sensing elements into separate light receiving areas, each partition pattern surrounding a corresponding color filter to be separate f

Abstract: A fan-out wafer level package includes: (1) a flexible substrate; (2) a semiconductor component embedded in the flexible substrate, the semiconductor component including an active surface that is exposed from the flexible substrate, the semiconductor component including a bonding pad adjacent to the active surface; (3) a stress buffer layer disposed over the flexible substrate and the semiconductor component, the stress buffer layer defining an opening exposing the bonding pad of the semiconductor component; and (4) an interconnect disposed over the stress buffer layer and including a portion extending into the opening of the stress buffer layer to electrically connect to the bonding pad of the semiconductor component.

Abstract: Provided are a semiconductor light-emitting array and a method of manufacturing the same. The manufacturing method includes forming a plurality of grooves in a region of a substrate and sequentially growing a first semiconductor layer, an active layer, and a second semiconductor layer on the substrate to form a light-emitting structure layer.

Abstract: A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first 10 semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated 15 circuit (PMIC).

Abstract: An ESD protective device for a MEMS element is described as having at least one first line; at least one n-region connected to the first line; at least one insulating region connected to the n-region; at least one p-region connected to the insulating region; at least one second line connected to the p-region; the n-region, the insulating region, and the p-region being situated on a substrate.

Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.