Abstract: A flexible display apparatus includes a flexible substrate including an active area and an inactive area, the inactive area comprising a first area disposed adjacent to the active area, a second area where a circuit board is disposed, and a bending area disposed between the first area and the second area, a first support layer disposed below the active area and the first area, and a second support layer disposed below the second area, an encapsulation layer disposed over the active area and the first area, and a polarization film disposed over the encapsulation layer. The polarization film extends up to at least a portion of the second area via the bending area, thereby reducing defects generated during bezel bending. Accordingly, a more stable display apparatus can be provided.

Abstract: A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding, and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.

Abstract: A display substrate, a method for manufacturing the same and a display device are provided. The display substrate includes a base substrate, first electrodes above the base substrate, and a light emitting layer disposed at a side of the first electrodes distal from the base substrate, the display substrate further includes signal lines extending in a first direction and fuse wires extending in a second direction, each fuse wire has a fusing point higher than that of the light emitting layer, the fuse wires are located at a side of the light emitting layer proximal to the base substrate and in contact with the light emitting layer, each fuse wire is electrically coupled to at least two signal lines, and an orthographic projection of at least one first electrode on the base substrate is located between orthographic projections of the at least two signal lines on the base substrate.

Abstract: A semiconductor substrate (1) has a front surface and a rear surface facing each other. A gate wiring (2) and first and second front surface electrodes (3,4) are provided on the front surface of the semiconductor substrate (1). The first and second front surface electrodes (3,4) are separated from each other by the gate wiring (2). An insulating film (7) covers the gate wiring (2). An electrode layer (8) is provided on the insulating film (7) and the first and second front surface electrodes (3,4) across the gate wiring (2). A rear surface electrode (9) is provided on the rear surface of the semiconductor substrate (1). A first plated electrode (10) is provided on the electrode layer (8). A second plated electrode (11) is provided on the rear surface electrode (9).

Abstract: An improved SiP structure includes one or more interposers positioned to form a center cavity into which one or more electronic components can be mounted. The improved SiP structure provides a reduced footprint using the one or more interposers and formed center cavity without the need of laser drilling, exposed molding, and/or double side molding.

Abstract: A stacked package structure has a metal casing, a stacked chipset, an encapsulation and a redistribution layer. The stacked chipset is adhered in the metal casing. The encapsulation is formed in the metal casing to encapsulate the stacked chip set, but a plurality of surfaces of the metal pads are exposed through the encapsulation. The redistribution layer is further formed on the encapsulation and electrically connects to the metal pads of the stacked chipset. Therefore, the stacked package structure includes the metal casing, so an efficiency of heat dissipation and structural strength are increased.

Abstract: A semiconductor device includes a semiconductor chip and a plurality of leads. The leads include a first lead including a supporting portion for mounting the semiconductor chip, and a projecting portion which projects in a first direction from the supporting portion. A second lead extends in a second direction non-parallel with the first direction, and one or more third leads extends in the second direction, such that a line extending in a third direction perpendicular to the first direction passes through the second lead and the one or more third leads. The second lead includes a first portion and a second portion, the first portion having a width larger than the second portion, the first portion having one side parallel to the first direction, and the first portion located between the second portion and the first lead.

Abstract: A light emitting stacked structure including a plurality of epitaxial sub-units disposed one over another, each epitaxial sub-unit configured to emit colored light having different wavelength band from each other, and a common electrode disposed between and connected to adjacent epitaxial sub-units, in which light emitting regions of the epitaxial sub-units overlap each other.

Abstract: The semiconductor package includes a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines.

Abstract: A semiconductor package includes a lead frame, a semiconductor device, a liquid metal conductor, and an encapsulation material. The semiconductor device is affixed to the lead frame. The liquid metal conductor couples the semiconductor device to the lead frame. The encapsulation material encases the semiconductor device, the liquid metal conductor, and at least a portion of the lead frame.

Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.

Abstract: A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.

Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer provided on a lower insulating layer. The horizontal semiconductor layer includes a cell array region and a connection region. An electrode structure is provided including electrodes. The electrodes are stacked on the horizontal semiconductor layer. The electrodes have a staircase structure on the connection region. A plurality of first vertical structures are provided on the cell array region to penetrate the electrode structure. A plurality of second vertical structures are provided on the connection region to penetrate the electrode structure and the horizontal semiconductor layer. Bottom surfaces of the second vertical structures are positioned at a level lower than a bottom surface of the horizontal semiconductor layer.

Abstract: A light emitting device includes a first light emitting element including a rectangular first light extraction surface, a second light emitting element including a rectangular second light extraction surface and emitting light having an emission peak wavelength different from an emission peak wavelength of the first light emitting element, and a light-transmissive member covering the first light extraction surface and the second light extraction surface. The light-transmissive member includes a first light-transmissive layer facing the first light extraction surface and the second light extraction surface, a wavelength conversion layer located on the first light-transmissive layer, and a second light-transmissive layer located on the wavelength conversion layer. The first light-transmissive layer contains a first matrix and first diffusive particles. The wavelength conversion layer contains a second matrix and wavelength conversion particles.

Abstract: A semiconductor package includes a connection member having first and second surfaces opposing each other and including a redistribution layer, an integrated circuit chip disposed on the first surface of the connection member, and including a plurality of units, at least one capacitor on the first surface of the connection member and in proximity to the integrated circuit chip, and an encapsulant on the first surface of the connection member and encapsulating the integrated circuit chip and the at least one capacitor, wherein the plurality of units include core power units selected from the group consisting of a central processing unit, a graphics processing unit, and an artificial intelligence unit, at least one of the core power units is disposed adjacent to one edge of the integrated circuit chip, and the at least one capacitor is disposed adjacent to the one edge of the integrated circuit chip.

Abstract: A semiconductor package includes a connection structure, a semiconductor chip, and an encapsulant. The connection structure includes an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer. The semiconductor chip has an active surface on which connection pads are disposed and an inactive surface opposing the active surface, and the active surface is disposed on the connection structure to face the connection structure. The encapsulant covers at least a portion of the semiconductor chip. The semiconductor chip includes a groove formed in the active surface and a dam structure disposed around the groove in the active surface.

Abstract: Openings, which are provided on the inner sides of anode electrodes formed in a display region, are larger than openings, which are provided on the inner sides of anode electrodes formed in a peripheral display region. A light-emitting layer formed in the display region has equal shape and equal size to a light-emitting layer formed in the peripheral display region.

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

Abstract: A manufacturing method of a chip package structure includes: dicing a wafer to separate chips formed thereon; mounting the chips on a carrier, wherein an active surface and pads of each chip are buried in an adhesive layer disposed on the carrier, and a top surface of the adhesive layer between the chips is bulged away from the carrier; forming an encapsulant to encapsulate the chips and cover the adhesive layer, wherein the encapsulant has a concave surface covering the top surface of the adhesive layer and a back surface opposite to the concave surface; removing the carrier and the adhesive layer; forming a first dielectric layer to cover the concave surface and the active surface; forming a patterned circuit layer on the first dielectric layer, to electrically connect to the pads through openings in the first dielectric layer; and forming a second dielectric layer on the patterned circuit layer.