Abstract: Embodiments of an apparatus with a thermal management technique utilizing a silicon heat sink and/or a phase-change material, as well as an assembling method thereof, are described. In one aspect, the apparatus comprises a main unit, a phase-change material and an enclosure enclosing the main unit and the phase-change material. The main unit comprises a substrate and at least one heat-generating device disposed on the substrate. The phase-change material is in direct contact with each heat-generating device of the at least one heat-generating device to absorb and dissipate heat generated by the at least one heat-generating device.

Abstract: A method of forming a custom module lid. The method may include placing a multichip module (MCM) between a module base and a temporary lid, target components are exposed through viewing windows in the temporary lid, a top surface of the target components is measured and mapped to create a target profile, the target profile is used to form custom pockets in a custom lid, and the custom pockets correspond to the target components.

Abstract: A semiconductor module comprising a plurality of electrically conductive top plates, an electrically conductive base plate, a plurality of semiconductor chips installed on the base plate, a first power supply connected to the plates, a second power supply connected to the plates and an electrically insulating outer casing component. The semiconductor chips are individually in contact with the top plates. Each semiconductor chip comprises a first electrode electrically coupled with the base plate, and a second electrical pole electrically coupled with the corresponding top plate. The first power supply connecting plate is equipped with protruding parts that are individually in electrical contact with the top plates. The second power supply connecting plate is electrically connected to the base plate. The outer casing component is used to integrate the first power supply connecting plate and the second power supply connecting plate. The outer casing component comprises at least one opening.

Abstract: Integrated circuit packages with openings surrounding a conductive via on a substrate layer are disclosed. An integrated circuit package may include a substrate layer with upper and lower surfaces. A conductive via may extend between the upper and lower surfaces of the substrate layer. The integrated circuit package further includes multiple openings in the substrate layer that may be distributed evenly in the substrate layer surrounding the conductive via. The multiple openings reduce signal insertion loss of the conductive via.

Abstract: A circuit device for controlling a transmission of a vehicle comprises an integrated circuit, which is mounted with a first surface on a first support surface of a circuit substrate and on a second surface opposite to the first surface comprises a heat-conducting surface for dissipating heat from the integrated circuit, in particular wherein the heat-conducting surface is designed as a contacting surface for contacting a heat sink.

Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.

Abstract: There is provided a power module package. The power module package includes: a base substrate provided with a pattern; a heat spreader formed by being stacked on an upper surface of the base substrate; and at least one first semiconductor device mounted on an upper surface of the heat spreader, wherein an outer circumferential surface of the heat spreader is provided with a coil.

Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Abstract: A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.

Abstract: A housing for an optoelectronic semiconductor component includes a housing body having a mounting plane and a leadframe with a first connection conductor and a second connection conductor. The housing body deforms the leadframe in some regions. The leadframe has a main extension plane which extends obliquely or perpendicularly with respect to the mounting plane. A semiconductor component having such a housing and a semiconductor chip and a method for producing a housing are also disclosed.

Abstract: A semiconductor device includes a chip having an active surface and a rear surface that is opposite to the active surface; a molding compound covering and encapsulating the chip except for the active surface; and a redistribution layer (RDL) on the active surface and on the molding compound. The RDL is electrically connected to the chip. The RDL includes an organic dielectric layer and an inorganic dielectric hard mask layer on the organic dielectric layer. The RDL further includes metal features in the organic dielectric layer and the inorganic dielectric hard mask layer.

Abstract: A semiconductor package including an integrated device, the package having a front side, a back side and side walls linking the front and back sides, wherein each side wall is coated, to at least 80% of its area, with a coating material different from the material(s) of the back and front sides. A method of manufacturing a semiconductor package by providing an assembly containing an array of the packages, the assembly having thickness d0 and being attached to a dicing tape of thickness dd, fabricating a set of first dicing streets with width w1 and depth d1<(d0+dd), filling the first dicing streets at least partially with a coating material, and fabricating, in the coating material in each first dicing street, a second dicing street with width w2?w1 and depth d2?d0 but <(d0+dd).

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: A multilayer electronic component may include: a multilayer body including a plurality of insulating layers; an internal coil part provided by electrically connecting respective conductive patterns disposed on the plurality of insulating layers to each other; and first and second external electrodes disposed on both end surfaces of the multilayer body, respectively. A perimeter of at least one conductive pattern disposed in peripheral regions of the multilayer body may be smaller than a perimeter of a conductive pattern disposed in a central region of the multilayer body.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.