Patents Examined by Alexander Oscar Williams
  • Semiconductor device having groove-shaped via-hole
    Patent number: 9406612
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 2, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Semiconductor device having groove-shaped via-hole
    Patent number: 9406611
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: August 2, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Semiconductor device having groove-shaped via-hole
    Patent number: 9406610
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: August 2, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Elastic wave device including multilayer metal film
    Patent number: 9406862
    Abstract: An elastic wave device includes a piezoelectric substrate including a primary surface and a first electrode which is provided on the primary surface of the piezoelectric substrate, which includes a first multilayer metal film including at least three metal films laminated in a bottom-to-top direction, and which includes at least an IDT film. The first multilayer metal film includes a Ti film as the topmost film and has a crystal orientation oriented in a predetermined direction so that the normal line direction of the plane of a Ti crystal of the Ti film coincides with the Z axis of a crystal of a piezoelectric body defining the piezoelectric substrate.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: August 2, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Chihiro Konoma
  • Semiconductor device having groove-shaped via-hole
    Patent number: 9406613
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 2, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Electronic devices with improved thermal performance
    Patent number: 9401316
    Abstract: Electronic devices with improved thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: July 26, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventor: Jaydutt Jagdish Joshi
  • Variable-size solder bump structures for integrated circuit packaging
    Patent number: 9385098
    Abstract: An integrated circuit package is described including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first plurality of variable-size solder bump structures. The first plurality of solder bump structures electrically couple the integrated circuit die to the substrate. The first plurality of variable-size solder bump structures are disposed on a bottom surface of the substrate. The first plurality of variable-size solder bump structures are sized to be substantially coplanar with a seating plane of the integrated circuit package.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 5, 2016
    Assignee: NVIDIA Corporation
    Inventors: Leilei Zhang, Zuhair Bokharey
  • Electronic device using method, electronic device and electronic apparatus adapted to switch operating modes
    Patent number: 9378702
    Abstract: An electronic device using method is provided. First, an electronic device and a display device are provided. Then, detecting whether the electronic device is electrically connected to the display device. If the electronic device is electrically connected to the display device, then a tilting angle of the electronic device is sensed. An operating mode of the electronic device corresponding to the display device is determined according to the tilting angle of the electronic device. In addition, an electronic device and an electronic apparatus having the electronic device is also provided.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 28, 2016
    Assignee: Wistron Corporation
    Inventors: Shiuan-De Chen, Tsung-Hsien Tsai, Chun-Peng Hsu, Hung-Li Chen
  • Fan out package structure
    Patent number: 9379041
    Abstract: Packages and methods of forming packages are disclosed. In an example, a structure comprises a die comprising an electrical pad on an active side, and an encapsulant laterally around the die and extending directly over the active side of the die. A conductive pattern is over the encapsulant, and the conductive pattern comprises a via in an opening through the encapsulant to the electrical pad. The via contacts the electrical pad. In some embodiments, a dielectric layer is over the encapsulant, and the conductive pattern is over the dielectric layer. In other embodiments, the encapsulant is a dielectric-encapsulant, and the conductive pattern adjoins the dielectric-encapsulant. In some embodiments, the encapsulant may be a photo-patternable material, a molding compound, or an Ajinomoto Build-up Film. The structure may further comprise additional dielectric layers and conductive patterns.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Szu-Wei Lu, Jing-Cheng Lin
  • Semiconductor device with at least one voltage-guided conductive filament
    Patent number: 9356001
    Abstract: A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second side, and includes at least a first contact pad located on the first side of the first semiconductor die. The second semiconductor die comprises a first and second side, and includes at least a second contact pad located on the first side of the second semiconductor die, wherein the first semiconductor die is stacked on the second semiconductor die and wherein the first side of the first semiconductor die faces the first side of the second semiconductor die. At least one voltage-guided conductive filament is created between the first contact pad and the second contact pad.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: May 31, 2016
    Assignee: HGST NETHERLANDS B.V.
    Inventor: Luiz M. Franca-Neto
  • Wiring structures including spacers and an airgap defined thereby, and methods of manufacturing the same
    Patent number: 9343355
    Abstract: A method of manufacturing a wiring structure may include forming a first conductive pattern on a substrate, forming a hardmask on the first conductive pattern, forming a first spacer on sidewalls of the first conductive pattern and the hardmask, forming a first sacrificial layer pattern on a sidewall of the first spacer, forming a second spacer on a sidewall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a third spacer on the second spacer, may be provided. The third spacer may contact an upper portion of the sidewall of the first spacer and define an air gap in association with the first and second spacers. The first spacer has a top surface substantially higher than a top surface of the first conductive pattern. The second spacer has a top surface substantially lower than the top surface of the first spacer.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: May 17, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chae-Ho Lim, Bo-Young Song, Cheol-Ju Yun
  • Semiconductor chip stack having improved encapsulation
    Patent number: 9343432
    Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: May 17, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chung-Sun Lee, Jung-Hwan Kim, Tae-Hong Kim, Hyun-Jung Song, Sun-Pil Youn
  • Pop joint through interposer
    Patent number: 9337135
    Abstract: A package includes a package component and an interposer over and bonded to the package component. The package component includes a solder region. The interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, with the first solder region in contact with a bottom end of the conductive pipe, and a through-opening in a center region of the interposer.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mirng-Ji Lii, Chien-Hsun Lee, Yu-Min Liang, Jiun Yi Wu
  • Three-dimensional semiconductor device
    Patent number: 9331082
    Abstract: A semiconductor device includes a stacked structure having first conductive layers stacked stepwise and first insulating layers interposed between the first conductive layers, wherein undercuts are formed under the first conductive layers and each of the first conductive layers includes a first region covered by the first conductive layer and a second region extending from the first region, contact pads coupled to the second regions of the respective first conductive layers, and a liner layer formed on the contact pads and filling the undercuts.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: May 3, 2016
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Ji Yeon Baek
  • Semiconductor package assembly with decoupling capacitor
    Patent number: 9331054
    Abstract: A semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 3, 2016
    Assignee: MEDIATEK INC.
    Inventors: Sheng-Ming Chang, Tung-Hsien Hsieh, Nan-Cheng Chen
  • Semiconductor device with a multilayer wire
    Patent number: 9331015
    Abstract: A semiconductor device includes a semiconductor structure having a first wire extending in a first direction, an intermetallic insulating layer covering the semiconductor structure, a via structure penetrating the intermetallic insulating layer, and a second wire extending on the intermetallic insulating layer in a second direction at a predetermined angle with respect to the first direction, the second wire being connected to the first wire through the via structure and including first and second portions on each other, and a protruding portion protruding from at least one of the first and second portions, the protruding portion being at a boundary of the first and second portions.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: May 3, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-hoon Han, Sung-jin Kim, Cheon-bae Kim, Won-chul Lee, Byung-hoon Cho
  • Resin-sealed semiconductor device and associated wiring and support structure
    Patent number: 9324636
    Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: April 26, 2016
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
  • Cooling assembly using heatspreader
    Patent number: 9318410
    Abstract: Various embodiments relate to a microchip die cooling assembly comprising a circuit board; a microchip having an exposed die attached to the circuit board; a heatspreader having a top side and a bottom side; a heat sink having a bottom side and a top side comprising a cooling structure; a first thermal interface material in contact with the exposed die and the bottom side of the heatspreader; and a second thermal interface material in contact with the top side of the heat spreader and the bottom side of the heat sink.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: April 19, 2016
    Assignee: Alcatel Lucent
    Inventors: Stefano F. De Cecco, Gregory W. Cheshire
  • Semiconductor device having a bulge portion and manufacturing method therefor
    Patent number: 9320173
    Abstract: A semiconductor device includes a base plate having a first major plane and a second major plane opposite to each other, and having a plurality of fins held upright on the first major plane and a bulge portion formed on the first major plane to encircle the plurality of fins, an insulation layer formed on the second major plane of the base plate, a circuit pattern fixed to the insulation layer, a semiconductor element connected to the circuit pattern, and a sealing resin sealing the insulation layer, the circuit pattern, and the semiconductor element. The bulge portion formed on the first major plane continuously encircles the plurality of fins, the bulge portion has a widthwise margin on an outer peripheral edge of the base plate, and the sealing resin covers an outer peripheral side face of the bulge portion and the widthwise margin.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: April 19, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kei Yamamoto, Kazuhiro Tada
  • Method and integrated device for analyzing liquid flow and liquid-solid interface interaction
    Patent number: 9310285
    Abstract: An Integrated Circuit (IC) chip with a lab-on-a-chip, a method of manufacturing the lab-on-a-chip and a method of using the lab-on-a-chip for fluid flow analysis in physical systems through combination with computer modeling. The lab-on-a-chip includes cavities in a channel layer and a capping layer, preferably transparent, covering the cavities. Gates control two dimensional (2D) lattice structures acting as heaters, light sources and/or sensors in the cavities, or fluid channels. The gates and two dimensional (2D) lattice structures may be at the cavity bottoms or on the capping layer. Wiring connects the gates and the 2D lattice structures externally.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Phaedon Avouris, Michael Engel, Claudius Feger, Ronaldo Giro, Rodrigo Ferreira, Mathias Steiner