Patents Examined by Alice W. Tang
  • Patent number: 6157044
    Abstract: A tunnel junction type Josephson device includes a pair of superconductor layers formed of a compound oxide superconductor material and an insulator layer formed between the pair of superconductor layers. The insulator layer is formed of a compound oxide which is composed of the same constituent elements as those of the compound oxide superconductor material of the superconductor layers but with an atomic ratio which does not present a superconductivity characteristics. In addition, the superconductor layers and the insulator layer are continuously formed while supplying oxygen.
    Type: Grant
    Filed: March 10, 1993
    Date of Patent: December 5, 2000
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hidenori Nakanishi, Saburo Tanaka, Hideo Itozaki, Shuji Yazu
  • Patent number: 5872368
    Abstract: The order parameter of a superconductor is reduced by injecting spin-polarized carriers into the superconductor. The reduction in the order parameter is used to modulate the critical current of the superconductor. In a typical embodiment, a current is caused to flow through a superconductor. Spin polarized electrons are then injected into the path of the current in the superconductor by biasing a magnetic metal with respect to a terminal of the superconductor. The bias current may be varied to modulate the injection and thus the flow of current through the superconductor.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: February 16, 1999
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Michael Osofsky, Robert J. Soulen, Jr., Raymond Auyeung, James S. Horwitz, Doug B. Chrisey, Mark Johnson
  • Patent number: 5859455
    Abstract: A non-volatile semiconductor memory cell includes a semiconductor substrate with a source and a drain formed therein. A channel is defined between the source and the drain. Atop the channel is a floating gate which is controlled by the X-control line and the Y-control line. The floating gate is uniquely disposed in the semiconductor substrate relative to the control lines such that when it is not addressed, the memory cell is isolated from the rest of the memory cells. As a consequence, the normal programming, deprogramming, and reading operations with other cells are not interfered. Moreover, the unique structure also facilitates the addressing of each of the memory cell.
    Type: Grant
    Filed: December 31, 1992
    Date of Patent: January 12, 1999
    Inventor: Shih-Chiang Yu
  • Patent number: 5844250
    Abstract: A process for manufacturing a field emission element including a substrate, and an emitter and a gate each arranged on the substrate is provided. The emitter is formed at at least a tip portion thereof with an electron discharge section, which is formed of metal or semiconductor into a monocrystalline structure or a polycrystalline structure preferentially oriented in at least a direction perpendicular to the substrate by deposition.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 1, 1998
    Assignee: Futaba Denshi Kogyo K.K,
    Inventors: Shigeo Itoh, Isao Yamada
  • Patent number: 5834851
    Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: November 10, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
  • Patent number: 5834800
    Abstract: A heterojunction bipolar transistor in an integrated circuit has intrinsic and extrinsic base portions. The intrinsic base portion substantially comprises epitaxial silicon-germanium alloy. The extrinsic base portion substantially comprises polycrystalline material, and contains a distribution of ion-implanted impurities. An emitter overlies the intrinsic base portion, and a spacer at least partially overlies the emitter. The spacer overhangs the extrinsic base portion by at least a distance characteristic of lateral straggle of the ion-implanted impurities.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: November 10, 1998
    Assignee: Lucent Technologies Inc.
    Inventors: Bahram Jalali-Farahani, Clifford Alan King
  • Patent number: 5831335
    Abstract: A semiconductor device comprising a silicon-series material layer and a laminate structure formed on the silicon-series material layer, the laminate structure being composed of a refractory metal thin film and/or a refractory metal silicide thin film, wherein a content of a halogen atom in each of the refractory metal thin film and/or the refractory metal silicide thin film is 1% by weight or less based on an amount of each of the refractory metal thin film and/or the refractory metal silicide thin film. In accordance with the present invention, there is also provided a process of producing such a semiconductor device.
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: November 3, 1998
    Assignee: Sony Corporation
    Inventor: Takaaki Miyamoto
  • Patent number: 5828121
    Abstract: This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: October 27, 1998
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, Jiunn Yuan Wu
  • Patent number: 5825049
    Abstract: A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.
    Type: Grant
    Filed: October 9, 1996
    Date of Patent: October 20, 1998
    Assignee: Sandia Corporation
    Inventors: Jerry A. Simmons, Marc E. Sherwin, Timothy J. Drummond, Mark V. Weckwerth
  • Patent number: 5821587
    Abstract: A semiconductor device provide with an ESD circuit including three active regions and element isolating regions formed on a semiconductor substrate in such a manner that the active regions are isolated from one another by the element isolating regions, source/drain diffusion regions respectively formed at the active regions, a first interlayer insulating film formed on the semiconductor substrate in such a manner that it covers the active regions and element isolating regions while being provided with first contact holes for exposing the diffusion regions, first lines formed on the first interlayer insulating film in such a manner that they are electrically connected to the diffusion regions via the first contact holes, respectively, a second interlayer insulating film formed over the entire exposed surface of the resulting structure obtained after the formation of the first line in such a manner that it has second contact holes for exposing the first line disposed over a central one of the active regions, an
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: October 13, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd
    Inventor: Jae Goan Jeong
  • Patent number: 5821562
    Abstract: Into an amorphous silicon film, catalyst elements for accelerating the crystallization are introduced. After patterning the amorphous silicon films in which the catalyst elements have been introduced into an island pattern, a heat treatment for the crystallization is conducted. Thus, the introduced catalyst elements efficiently diffuse only inside the island-patterned amorphous silicon films. As a result, a high-quality crystalline silicon film, having the crystal growth direction aligned in one direction and having no grain boundaries, is obtained. Using the thus formed crystalline silicon film, semiconductor devices having a high performance and stable characteristics are fabricated efficiently over the entire substrate, irrespective of the size of the devices.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: October 13, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoki Makita, Takashi Funai, Yoshitaka Yamamoto, Yasuhiro Mitani, Katsumi Nomura, Tadayoshi Miyamoto, Takamasa Kosai
  • Patent number: 5814895
    Abstract: In a static random access memory (SRAM), a memory cell ratio is increased without deteriorating an integration degree of this SRAM. The static random access memory is arranged by: trenches formed in a semiconductor substrate and an insulating layer for isolating elements within a memory cell forming region; one pair of word transistors; one pair of driver transistors for constituting a flip-flop by forming channel regions of the driver transistors in side surfaces of the trenches and by cross-connecting gate electrodes thereof and drain electrodes thereof at one pair of input/output terminals of the flip-flop; and one pair of word transistors connected between the one pair of input/output terminals of the flip-flop and a bit line.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: September 29, 1998
    Assignee: Sony Corporation
    Inventor: Teruo Hirayama
  • Patent number: 5804877
    Abstract: Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs 22, whereby a reliable and stable electrical contact is established to the GaAs surface 20 and whereby Ti does not generally react with the In.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: September 8, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Clyde R. Fuller, Joseph B. Delaney, Thomas E. Nagle
  • Patent number: 5801410
    Abstract: A ferroelectric capacitor includes a substrate and a capacitor electrode on the substrate. A ferroelectric layer is provided on the first capacitor electrode, and a first insulating layer on the ferroelectric layer has a first contact hole therein exposing a portion of the ferroelectric layer. A second capacitor electrode on the first insulating layer makes contact with the ferroelectric layer through the first contact hole. In addition, the second capacitor electrode includes an extension that extends across the first insulating layer away from the first contact hole. A second insulating layer on the second capacitor electrode opposite the substrate has a second contact hole therein exposing a portion of the second insulating capacitor electrode extension opposite the first insulating layer. A conductive line on the second insulating layer makes contact with the exposed portion of a second capacitor electrode extension opposite the insulating layer through the second contact hole.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: September 1, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yun-Gi Kim
  • Patent number: 5793114
    Abstract: A method and structure for self-aligned zero-margin contacts to active and poly-1, using silicon nitride (or another dielectric material with low reflectivity and etch selectivity to oxide) for an etch stop layer and also for sidewall spacers on the gate.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: August 11, 1998
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Loi N. Nguyen, Robert Louis Hodges
  • Patent number: 5793080
    Abstract: A nonvolatile memory device includes a semiconductor substrate of a first conductivity type; a gate insulating film formed on the substrate; a floating gate having a first region and a second region, the first region lying flat over the gate insulating film and the second region being extended from a first end portion of the first region and perpendicular to the first region; a control gate extending parallel to the second region of the floating gate, lying over the second end portion of the first region of the floating gate and perpendicular to the first region; an inter-insulating layer disposed between the floating gate and the control gate; a first spacer formed at a side wall of the second region of the floating gate and a second spacer formed at a side wall defined by the floating gate and the control gate; a high density source region of a second conductivity type formed in the substrate, being disposed a thickness of the first spacer distant from the floating gate; a first high density drain region of
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: August 11, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventor: Hyun Sang Hwang
  • Patent number: 5780910
    Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.
    Type: Grant
    Filed: July 17, 1996
    Date of Patent: July 14, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Naotaka Hashimoto, Yutaka Hoshino, Shuji Ikeda
  • Patent number: 5767560
    Abstract: A photoelectric conversion device including: a photoelectric conversion portion having a light absorbing layer disposed between charge injection inhibition layers and having a predetermined forbidden band width Eg.sub.1, and a carrier multiplication portion including a single or a plurality of inclined band gap layers, the inclined band gap layer including a minimum forbidden band width Eg.sub.2 and a maximum forbidden band width Eg.sub.3 which are disposed to be in contact with each other to form a hetero junction and having, at the two ends thereof, forbidden band widths Eg.sub.4 which holds a relationship Eg.sub.2 <Eg.sub.4 <Eg.sub.3 in such a manner that the forbidden band width is continuously changed from the two forbidden band widths Eg.sub.2 and Eg.sub.3 to the forbidden band width Eg.sub.4, and the energy step in a conductive band of the hetero junction portion is larger than the energy step in a valence electron band, wherein at least the minimum forbidden band width Eg.sub.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: June 16, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Ihachiro Gofuku
  • Patent number: 5767540
    Abstract: A hetero-junction bipolar transistor comprising a collector layer, a base layer and an emitter layer formed stepwise in this order wherein the emitter layer comprises a plurality of layers including an AlGaAs layer, and a passivation layer is formed at a stepwise portion between the base layer and the emitter layer, and of a material having a bandgap larger than that of the base layer, and provided with a phosphide layer on the surface thereof.
    Type: Grant
    Filed: February 22, 1996
    Date of Patent: June 16, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masafumi Shimizu
  • Patent number: 5763897
    Abstract: In the structure of the device of the invention, a supper-lattice buffer layer is formed between the undoped layer and doped layers. This super-lattice buffer layer serves as a carrier-piling up layer in place of the undoped layer in the conventional device. Thus, the amounts of the piled-up carriers in the undoped layer can be greatly reduced and hence no band filling effect occurs in the undoped layer. Consequently, an optical device having a flat frequency characteristic can be produced without losing its modulating characteristic.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: June 9, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hirohisa Sano, Tatemi Ido