Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration using a lattice determining surrogate substrate and a mesa-forming deep etch processing sequence and then inverted onto a new permanent substrate member and the surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Fabrication of the device from two possible indium-inclusive semiconductor materials and a particular gate metal alloy is also disclosed.

Abstract: Integrated voltage divider comprising partial resistors (R1 ,R2) formed of paths of polycrystalline semiconductor material applied over a dielectric layer (4) on a semiconductor substrate (5). Under the paths, each forming a partial resistor (R1,R2) in the semiconductor substrate (5), a well (6 and 7 respectively) is formed having a conductivity type opposite to the conductivity type of the semiconductor substrate (5). The total surfaces of the paths forming the partial resistors (R1,R2) are dimensioned so that their ratio equals the inverse ratio of the resistor values of the two partial resistors (R1 ,R2).

Abstract: The incorporation of an aluminum arsenide (AlAs) buffer layer in a gallium arsenide (GaAs) field effect transistor (FET) structure is found to improve the overall device performance, particularly in the high temperature operating regime. Similar characteristics may be obtained from devices fabricated with an Al.sub.x Ga.sub.1-x As 0.2.ltoreq.x.ltoreq.1 barrier layer. At temperatures greater than 250.degree. C., the semi-insulating gallium arsenide substrate begins to conduct significant amounts of current. The highly resistive AlAs buffer layer limits this increased conduction, thus permitting device operation at temperatures where parasitic leakage currents would impede or prevent device operation. Devices fabricated with AlAs buffer layers exhibited lower drain parasitic leakage currents and showed improved output conductance characteristics at 350.degree. C. ambient temperature.

Abstract: This invention relates to a semiconductor device comprising at least one p-n junction. The junction is formed from a "p" semiconductor contacting an "n" semiconductor. Said device characterized in that at least one of said "p" or "n" semiconductor is a nanoporous crystalline semiconducting material. These nanoporous materials have an intracrystalline nanopore system whose pores are crystallographically regular and have an average pore diameter of about 2.5 to about 30 .ANG.. Additionally, they have a band gap of greater than 0 to about 5 eV which band gap can be modified by removing a portion of the templating agent from the pore system of the materials. The materials which have these properties include, metal polychalcogenide compounds, metal sulfides and selenides, metal oxides, and metal oxysulfides. These materials can be used in a large variety of semiconducting devices such as light emitting diodes, bipolar transistors, etc. A process for preparing these nanoporous materials is also presented.

Abstract: A lattice matching device includes a substrate having thereon monocrystal regions having different lattice mismatches with respect to a LnBa.sub.2 Cu.sub.3 O.sub.x superconductor. A superconducting thin film is formed on the substrate, which film consists essentially of a superconductor of LnBa.sub.2 Cu.sub.3 O.sub.x wherein Ln represents yttrium or a lanthanide, and 6<x<7. The first and second superconducting thin film portions have different axes of orientation perpendicular to a main surface of the substrate, and arranged in contact with each other or at a distance which allows transmission of electron pairs from one to another.

Abstract: A method is provided for forming a radiation hard dielectric region of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide region, a gate oxide layer and an interlevel dielectric layer are formed over the integrated circuit. Silicon ions are implanted separately into the field oxide region, gate oxide layer and interlevel dielectric layer to a sufficient dosage of less than or equal to approximately 1.times.10.sup.14 /cm.sup.2 to form electron traps to capture radiation induced electrons. This method allows for selective enhancement of radiation hardness of a portion of a circuit, thus providing an on-chip "dosimeter" which can be used to compensate the circuit for the loss of performance due to ionizing radiation.

Abstract: A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

Abstract: A II-VI group compound semiconductor device having a p-type Zn.sub.x Mg.sub.1-x S.sub.y Se.sub.1-y (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) semiconductor layer, on which an electrode layer is formed with at least metallic nitride layer lying between the semiconductor layer and the electrode layer.

Abstract: A thin-film transistor device comprising a pixel section including a plurality of pixel electrodes arranged in rows and columns on a substrate and a plurality of thin-film transistors of reverse stagger type, connected as switching elements to the pixel electrodes, respectively, and a drive section including a plurality of thin-film transistors of coplanar type, each having a gate insulating film, for driving the thin-film transistors of the reverse stagger type. A lower insulating film is located beneath the thin-film transistors of the reverse stagger type. The lower insulating film and the gate insulating films of the thin-film transistors of the coplanar type are formed of a first insulating film provided on the substrate.

Abstract: The present invention is directed to methods and apparatus for accurately detecting light energy of a signal of interest (e.g., a laser pulse) even when the signal-to-noise ratio is relatively low. The present invention is further directed to accurate detection of a signal of interest even when either or both the signal of interest and background illumination vary across plural pixels of an imaging an array. For example, a signal of interest can be accurately detected even in the presence of pixel response non-uniformity and fixed pattern noise, or when the incident signal of interest is not confined laterally to a single pixel.

Abstract: A heterojunction FET includes an electron supply layer formed on a non-doped semiconductor layer serving as a channel forming layer and a current path forming layer formed on the electron supply layer. The electron supply layer has an energy band gap greater than the non-doped semiconductor layer and its portion under a gate electrode is always depleted at any gate bias voltage in a bias voltage range for operating of the field effect transistor. The current path forming layer has a larger electron mobility than the electron supply layer. The gate electrode is formed on the current supply layer. Under a high gate bias voltage condition, parallel conduction does not occur in the electron supply layer but does occur in the current path forming layer. Since the current path forming layer has a larger carrier mobility than the electron supply layer, the mutual conductance value is kept high.

Abstract: Parts of the emitter and base of a vertical bipolar transistor adjoin a field-isolation region to form a walled-emitter structure. The transistor is furnished with extra doping in the collector and, optionally, in the base. The extra collector doping is provided along collector-base junction below the intrinsic base to create a special collector zone spaced laterally apart from the field-isolation region. The presence of the special collector zone causes the intrinsic base to be thinner, thereby raising the cutoff frequency and overall current gain. The extra base doping is provided in the intrinsic base along the field-isolation region to improve the transistor's breakdown voltage and leakage current characteristics.

Abstract: A superluminescent diode includes a semiconductor substrate of a first conductivity type. A lower cladding layer of the first conductivity type is provided on the semiconductor substrate. An active layer is provided on the lower cladding layer. An upper cladding layer of a second conductivity type opposite to the first conductivity type is provided on the active layer. A current blocking layer of the first conductivity type is buried in the upper cladding layer. The current blocking layer has a stripe-shaped groove serving as a current-injection region. The current-injection region is formed in a manner that it extends from an end face of a chip to the inside of the chip, and has a length shorter than that of the chip. The current blocking layer is made of a material having a band gap energy not greater than that of the active layer and a refractive index not smaller than that of the active layer so that light advancing in the active layer is absorbable.

Abstract: The SQUID device consists of a loop of superconducting film material applied to the face of a substrate, the loop having a first width. A Josephson Junction is formed in the loop of the superconducting film material by pads of superconducting film material overlying one another and separated by a layer of insulating material. The pads have a second width larger than the first width. To increase the gain and improve the signal-to-noise ratio, the SQUID device may include a plurality of SQUID loops connected to one another in parallel. These loops may be overlie one another, or be adjacent to one another, or both, and may be either conventional SQUID loops or the improved SQUID loops with wide pads.

Abstract: A programmable integrated circuit for forming conductive links includes a heat-generating programming structure through which current flows upon application of a programming voltage to heat the region around the programming structure. A programmable link structure including two conductors separated by a transformable insulator is in thermal communication with the programming circuit. When current flows through the programming circuit, the programmable link structure is heated. The heat causes the transformable insulator to break down such that a permanent conductive link is formed between the two conductors of the programmable link structure. During programming, a programming conductor is cut symmetrically about the programming structure.

Abstract: In an electronic device using lead zirconate titanate (PZT) or lanthanum lead zirconate titanate (PLZT) as the main insulating material, a PZT film or a PLZT film is formed on a sub-insulating layer consisting essentially of lead titanate, lanthanum lead titanate, barium titanate, strontium titanate, barium strontium titanate, lead zirconate, or lanthanum lead zirconate. In an MIS structure, a semiconductor, the sub-insulating layer, the PZT film and metal are deposited in order. In a capacitor, the sub-insulating layer and the PZT film are sandwiched between a pair of electrodes. The sub-insulating layer improves crystallinity of PZT or PLZT, and the dielectric constant. An oxide of Pb, La, Zr or Ti can be added as the sub-insulating layer in order to further suppress current leakage.

Abstract: A DRAM device includes bit lines formed on an interlayer insulation film which covers gate electrodes on an insulation film on a semiconductor substrate. Each bit line is in contact with the corresponding source region formed in the substrate through an opening in the insulation films. Another insulation film is formed so as to cover the bit lines. A storage electrode is formed on the insulation film covering the bit line, and is in contact with a drain region in the substrate through another opening in the insulation films. The bit line has a vertical layer level lower than that of the storage electrode. The storage electrode is covered with a dielectric film, which is covered with an opposed electrode.

Abstract: A field emission cathode device comprising a semiconductor substrate, a semiconductor cathode electrode layer, emitter tips formed on the cathode electrode layer to emit electrons therefrom, and a gate electrode layer formed on an insulating layer. Each of the emitter tips is arranged in the aligned apertures of the gate electrode layer and the insulating layer. To electrically isolate two adjacent cathode electrode lines from each other, the cathode electrode layer is made of a semiconductor having a conductivity type different from that of the substrate. Alternatively, the cathode electrode is made of a semiconductor having the same conductivity type as that of the substrate, and in this case, a portion between two adjacent cathode electrode lines is made of a heavily doped semiconductor so as to electrically isolate two adjacent cathode electrodes.

Abstract: This invention provides a stacked gate flash memory cell structure and a method for forming the stacked gate flash memory structure. The invention uses a large angle ion implant beam without wafer rotation to form the source and drain regions of the memory cell. A low doped region is formed between an edge of the first gate electrode and an edge of either the source or drain regions. The tunnel dielectric is formed directly above the low doped region. The width of the low doped region is controlled by the angle of the large angle ion implant beam and can be very accurately controlled. The tunnel dielectric is formed independently of the gate dielectric and the thickness of each can be optimized. The tunnel dielectric area can be made very small which improves reliability and reduces the voltage necessary to program and erase the memory cell.

Abstract: A photovoltaic diode unit cell (10) includes a first layer (14) having a first type of electrical conductivity and a second layer (16) of Group II-VI material having a second type of electrical conductivity that differs from the first type. The first layer and the second layer are coupled together so as to form a photovoltaic junction (15) therebetween. The photovoltaic junction is coupled via electrical interconnects (18, 20, 22) to a readout 24 and collects first charge carriers resulting from an absorption of IR radiation within the layer 14. The junction also collects second charge carriers resulting from the absorption of visible light in a region of highly graded crystal potential formed, in a Liquid Phase Epitaxy (LPE)-grown embodiment of this invention, at an interface of a substrate and the first layer. The substrate is subsequently removed, preferably by a mechanical operation followed by a wet chemical etch, to expose the region of highly graded crystal potential.