Patents Examined by Alice W. Tang
  • Patent number: 5561318
    Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between and over conductors 24 and drying the wet gel to create at least porous dielectric sublayers 28 and 29. By varying the composition of the solutions, gelling conditions, drying temperature, composition of the solvents in the wet gel, or a combination of these approaches, the porosity of the sublayers may be tailored individually. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 1, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Bruce E. Gnade, Chih-Chen Cho, Douglas M. Smith
  • Patent number: 5559360
    Abstract: An inductor fabricated for semiconductor use is disclosed. The inductor is formed with a multi-level, multi-element conductor metallization structure which effectively increases conductance throughout the inductor thereby increasing the inductor's Q. The structure of the inductor may also provide for routing the current flowing through the multi-level, multi-element conductors in a way that increases the self inductance between certain conductive elements, thereby increasing the inductor's total inductance.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: September 24, 1996
    Assignee: Lucent Technologies Inc.
    Inventors: Tzu-Yin Chiu, Frank M. Erceg, Duk Y. Jeon, Janmye Sung
  • Patent number: 5552374
    Abstract: A superconducting device comprises a thin superconducting channel formed of an oxide superconductor, a superconducting source region and a superconducting drain region formed of an oxide superconductor at the both ends of the superconducting channel which connects the superconducting source region and the superconducting drain region, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region. The superconducting device further includes a gate electrode through a gate insulator on the superconducting channel for controlling the superconducting current flowing through the superconducting channel. The length of the gate electrode ranges from one third of the length of the superconducting channel to one and a half length of the superconducting channel.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: September 3, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: So Tanaka, Michitomo IIyama
  • Patent number: 5548131
    Abstract: A light-emitting device formed by applying a crystal formation process to a substrate with a free surface on which provided, in mutually adjacent manner, are a non-nucleation surface and a nucleation surface with a nucleation density larger than that of the non-nucleation surface, wherein the nucleation surface is provided in an oblong form.
    Type: Grant
    Filed: September 12, 1994
    Date of Patent: August 20, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Tokunaga, Hideshi Kawasaki
  • Patent number: 5548132
    Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 20, 1996
    Assignee: Micron Technology, Inc.
    Inventors: Shubneesh Batra, Monte Manning, Sanjay Banerjee, John Damiano, Jr.
  • Patent number: 5541442
    Abstract: An improved configuration of a capacitor formed with FET technology and a resistor and/or conductor is provided. In this configuration a capacitor is formed in which the diffusion zone of the substrate is used as one plate of the capacitor and what would normally be the gate electrode of an FET is used as the other plate of the capacitor, with the two plates being separated by a conventional thin dielectric gate oxide layer. An insulator, such as silicon dioxide overlays the gate electrode, and electrical connections to the gate electrode and diffusion zone are made through the insulator to allow the two plates of the capacitor to be connected to various devices or components as required. The top surface of this insulation layer is also used to form metal resistors. Depending on the value of required resistance, a second insulating layer may be used and a second level of metal used to connect segments of the resistors formed on the first layer of metal to form a longer resistor.
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: July 30, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard F. Keil, Ram Kelkar, Ilya I. Novof, Jeffery H. Oppold, Kenneth D. Short, Stephen D. Wyatt
  • Patent number: 5539221
    Abstract: An avalanche photodiode is provided which consists of a staircase APD with a periodic multilayer structure graded in composition from InAlAs to InGa.sub.x Al.sub.(1-x) As (x>0.1) as the multiplication layer to improve the dark current characteristic. Another photodiode with separate photoabsorption and multiplication regions is provided with an electric-field relaxation layer whose bandgap is wider than that of the photoabsorption and has a triple structure with a highly-doped layer sandwiched between lightly-doped layers. This photodiode incorporates in detail on an n-type InP substrate, an avalanche multiplication layer 13 of a periodic multilayer structure graded in composition from n.sup.- -InAlAs to InGa.sub.x Al.sub.(1-x) As, a p.sup.- -InGaAs photoabsorption layer 17, and an InP electric-field relaxation triple layer 16 consisting of n.sup.-, p.sup.+, and p.sup.- layers between the avalanche multiplication layer 13 and the photoabsorption layer 17.
    Type: Grant
    Filed: April 7, 1994
    Date of Patent: July 23, 1996
    Assignee: NEC Corporation
    Inventors: Masayoshi Tsuji, Kikuo Makita
  • Patent number: 5530293
    Abstract: An insulator for covering an interconnection wiring level in a surface thereof on a semiconductor substrate containing semiconductor devices formed by curing a flowable oxide layer and annealing is provided. The annealing is carried out in the presence of hydrogen and aluminum to obtain a dielectric constant of the oxide layer to a value below 3.2. Also provided is electrical insulation between neighboring devices using the flowable oxide which is cured and annealed. In this case, the annealing can be carried out in hydrogen with or without the presence of aluminum.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: June 25, 1996
    Assignee: International Business Machines Corporation
    Inventors: Stephan A. Cohen, Vincent J. McGahay, Ronald R. Uttecht
  • Patent number: 5523615
    Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for sample, between patterned conductors 24. The process may include baking the structure in a reducing atmosphere, preferably a forming gas, to dehydroxylate the pore surfaces. The process may include baking the structure in a halogen-containing atmosphere to bond halogens to the pore surfaces. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 4, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Chi-Chen Cho, Bruce E. Gnade, Douglas M. Smith
  • Patent number: 5523619
    Abstract: A memory cube comprising a plurality of memory chips, each having a plurality of data storage devices, is provided with an auxiliary chip having inactive line termination circuits and the auxiliary chip or chips are formed as part of the memory cube structure and disposed among the memory chips on an interleave basis. The auxiliary circuit chips are provided with external terminals connected to memory input leads, control leads and data write leads, in close proximity to the termination point of the leads. A decoupling capacitor, integrated in the auxiliary circuit chip, is connected to the power bus in the memory cube structure and eliminates extraneous noise problems occurring with discrete capacitors external to the cube. A heating resistor is provided on the auxiliary circuit chip to maintain the cube structure at a near constant temperature. Temperature sensing diodes are incorporated in the auxiliary chip to provide an accurate mechanism for sensing the temperature internal to the cube.
    Type: Grant
    Filed: November 3, 1993
    Date of Patent: June 4, 1996
    Assignee: International Business Machines Corporation
    Inventors: Michael F. McAllister, James A. McDonald, Gordon J. Robbins, Madhavan Swaminathan, Gregory M. Wilkins
  • Patent number: 5521422
    Abstract: A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: May 28, 1996
    Assignee: International Business Machines Corporation
    Inventors: Jack A. Mandelman, Brian J. Machesney, Hing Wong, Michael D. Armacost, Pai-Hung Pan
  • Patent number: 5519238
    Abstract: A new method to produce a microminiturized capacitor having a regular microscopic ripple surface electrode is achieved by depositing a first polysilicon layer over a suitable insulating base. A resist layer is formed over the first polysilicon layer. The resist layer is exposed through a mask having a pattern of regular spaced openings in the areas of the planned capacitor to radiant energy in sufficient quantity to under expose, out of focus expose or a combination of under expose and out of focus expose the resist layer. The mask is shifted a fixed and short distance. The resist layer is exposed through the shifted mask to radiant energy in sufficient quantity to under expose or out of focus expose, or a combination of under expose or out of focus expose the resist layer again and in a different location. The shifting of the mask and exposing resist steps are repeated until a pattern of the regular microscopic ripple has been formed in the resist layer.
    Type: Grant
    Filed: February 5, 1993
    Date of Patent: May 21, 1996
    Assignee: Industrial Technology Research Institute
    Inventor: Chih-Yuan Lu
  • Patent number: 5519234
    Abstract: An integrated circuit includes a layered superlattice material having the formula A1.sub.w1.sup.+a1 A2.sub.w2.sup.+a2 . . . Aj.sub.wj.sup.+aj S1.sub.x1.sup.+s1 S2.sub.x2.sup.+s2 . . . Sk.sub.xk.sup.+ak B1.sub.y1.sup.+b1 B2.sub.y2.sup.+b2 . . . Bl.sub.yl.sup.+bl Q.sub.z.sup.-2, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . Bl represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in non-volatile memories. Others are high dielectric constant materials that do not degrade or breakdown over long periods of use and are applied in volatile memories.
    Type: Grant
    Filed: November 18, 1993
    Date of Patent: May 21, 1996
    Assignee: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Michael C. Scott, Larry D. McMillan
  • Patent number: 5517044
    Abstract: A non-volatile semiconductor memory device is constituted by a plurality of thin film memory transistors, each having a control gate electrode formed on an insulating film on a semiconductor substrate, a first gate insulating film covering said control gate electrode, a floating gate electrode formed on said first gate insulating film, a second gate insulating film provided on said floating gate electrode, a channel region of a first conductivity type semiconductor film provided on said second gate insulating film, and source/drain regions of a second conductivity type semiconductor film formed with said channel region being interposed therebetween. A memory device such as an EPROM or FEPROM is formed by using the above thin film memory transistors. The invention provides a semiconductor memory device which operates at a high speed and in which it is possible to achieve a high integration.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: May 14, 1996
    Assignee: NEC Corporation
    Inventor: Shoji Koyama
  • Patent number: 5514897
    Abstract: A graduated concentration profile is used for defining a buried isolation region in a semiconductor device. Smaller concentrations of dielectric-defining particles are used for implantation at the deepest levels of the isolation region in order to reduce the defect density in an overlying epi layer.
    Type: Grant
    Filed: November 10, 1994
    Date of Patent: May 7, 1996
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventor: Tatsuo Nakato
  • Patent number: 5512770
    Abstract: This invention describes a device structure and a method of forming the device structure using a polysilicon spacer formed on the edges of the gate electrode forming a gate structure with a cavity. The channel area is self aligned through this cavity. A fully overlapped Lightly-Doped-Drain structure is used to improve device characteristics for submicron devices. A deep boron implant region, self aligned through the gate structure, is used to improve punch through voltage.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: April 30, 1996
    Assignee: United Microelectronics Corporation
    Inventor: Gary Hong
  • Patent number: 5512769
    Abstract: A high breakdown voltage semiconductor device is constituted, in either a semiconductor substrate or a lightly doped well diffused layer having deep diffusion depth, of a heavily doped diffused layer as a heavily doped drain diffused layer, a lightly doped diffused layer having deeper diffusion depth that the heavily doped diffused layer, and a lightly doped diffused layer adjacent to the heavily doped diffused layer called as an offset diffused layer. The heavily doped diffused layer functions as a part of the drain diffused layer, and has depth around 0.3 to 0.6 micron meter, and impurity concentration of 10.sup.19 to 10.sup.20 impurities/cm.sup.3. The width of the heavily doped diffused layer is set to 4 to 5 micron meters or greater. If the width of the heavily doped diffused layer is set less than this value, the breakdown voltage at an edge is lowered, and thereby impairment of the breakdown voltage occurs. The lightly doped diffused layer also functions as a part of the drain diffused layer.
    Type: Grant
    Filed: September 27, 1994
    Date of Patent: April 30, 1996
    Assignee: Matsushita Electronics Corporation
    Inventor: Masaharu Yamamoto
  • Patent number: 5510648
    Abstract: An insulated gate semiconductor device (10) having a pseudo-stepped channel region (20B) between two P-N junctions (21B and 22B). The pseudo-stepped channel region (20B) is comprised of an enhancement mode portion (26B) and a depletion mode portion (28B), the enhancement mode portion (26B) being more heavily doped than the depletion mode portion (28B). One P-N junction (21B) is formed at an interface between a source region (18B) and the enhancement mode portion (26B). The enhancement mode portion (26B) has a substantially constant doping profile, thus slight variations in the placement of the source region (18B) within the enhancement region (26B) do not result in significant variations in the threshold voltage of the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) is well suited for the design of low voltage circuits because of the small variations of the threshold voltage.
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: April 23, 1996
    Assignee: Motorola, Inc.
    Inventors: Robert B. Davies, Peter J. Zdebel, Juan Buxo
  • Patent number: 5506426
    Abstract: Chalcopyrite compound semiconductor thin films represented by I-III-VI.sub.2-x V.sub.x or I-III-VI.sub.2-x VII.sub.x, and semiconductor devices having a I-III-VI.sub.2 /I-III-VI.sub.2-x V.sub.x or I-III-VI.sub.2 /I-III-VI.sub.2-x VII.sub.x chalcopyrite homojunction are provided. Such chalcopyrite compound semiconductor thin films are produced by radiating molecular beams or ion beams of the I, III, VI, and V or VII group elements simultaneously, or by doping I-III-VI.sub.2 chalcopyrite thin films with VII-group atoms after the formation thereof. Pollution-free solar cells are also provided, which are formed by the steps of forming a structure of a lower electrode, a chalcopyrite semiconductor thin film, and an upper electrode and radiating accelerated ion beams of a V, VII, or VIII group element thereto.
    Type: Grant
    Filed: May 12, 1993
    Date of Patent: April 9, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigemi Kohiki, Takayuki Negami, Mikihiko Nishitani, Takahiro Wada
  • Patent number: 5500537
    Abstract: A field effect transistor has a channel between a source electrode and a drain electrode made from an organic semiconductor. In one form of the invention, the channel is a mixture of at least two different organic compounds. In another form of the invention, the channel is a lamination of at least two films of different organic compounds. The channel can also be a .pi.-conjugated block copolymer of at least two different types of monomers.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: March 19, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Tsumura, Hiroyuki Fuchigami, Hideharu Nobutoki, Hiroshi Koezuka