Abstract: A superconducting tunnel element, having a plurality of super conductors separated by barriers, the superconductors each comprising two physically separate but electrically connected superconducting layers and one insulated control layer. As a result, summation of the detection capacity or of the transmitting intensity becomes possible. Also, the simultaneous detection or transmission is permitted on arbitrary different frequencies or a summation of the signal intensity is possible in the case of SQUID-systems.

Abstract: A lateral bipolar transistor has an extrinsic base layer on either side of a centrally disposed emitter layer and an intrinsic base and a collector oriented perpendicularly to the extrinsic base and collector layers.

Abstract: An ultra-high-speed photoconductive device is described which comprises a homoepitaxial semi-insulating III-V layer, or body, upon which ohmic/conductive contacts, or strips, separated by a small gap, are formed. The semi-insulating body, or layer, is produced by low temperature growth of III-V compounds by MBE. In a GaAs embodiment, the layer is grown under arsenic stable growth conditions, at a substrate temperature preferably in the range of 150.degree. to about 300.degree. C.

Abstract: A method and resulting ohmic contact structure between a high work function metal and a wide bandgap semiconductor for which the work function of the metal would ordinarily be insufficient to form an ohmic contact between the metal and the semiconductor. The structure can withstand annealing while retaining ohmic characteristics. The ohmic contact structure comprises a portion of single crystal wide bandgap semiconductor material; a contact formed of a high work function metal on the semiconductor portion; and a layer of doped p-type semiconductor material between the single crystal portion and the metal contact. The doped layer has a sufficient concentration of p-type dopant to provide ohmic behavior between the metal and the semiconductor material.

Abstract: A superconducting tunnel junction radiation sensing device includes first and second superconductor electrodes and a tunnel barrier layer interposed therebetween. The tunnel barrier layer is made up of a thin-wall portion and a thick-wall portion each formed of a semiconductor or an insulator, and each having opposite surfaces respectively contacting the first and second superconductor electrodes, and each extending adjacent each other in a same horizontal plane between the first and second electrodes. The thick-wall portion has a vertical thickness which is at least twice that of the thin-wall portion. Furthermore, the thickness of the thin-wall portion is such that a tunnel effect is enabled therethrough form the first electrode to the second electrode, and the thickness of the thick-wall portion is such that a tunnel effect is substantially prohibited therethrough from the first electrode to the second electrode.

Abstract: The invention provides a semiconductor device equipped with a high-voltage MISFET capable of forming a push-pull circuit on one chip by optimizing a junction-separation structure. In an n-channel MOSFET, when a potential is applied to the gate electrode, to the source electrode, and across the drain electrode and the semiconductor substrate to expand the depletion layer from the junction face of a semiconductor substrate and a well formed thereon, the leading edge of the depletion layer does not reach a low-concentration drain diffusion region formed on the well. When a potential is applied to the drain electrode, to the semiconductor substrate, and across the source electrode and the gate electrode to expand a depletion layer from the junction face of the low-concentration drain diffusion region and the well, and a depletion layer from the junction face of semiconductor substrate and the well, the depletion layers are connected with each other.

Abstract: A lead-on-chip (LOC) semiconductor device (10) has an integral decoupling capacitor in the form of a capacitor tape (20) attached to an active surface (14) of a semiconductor die (12). The capacitor tape includes two adhesive layers (22 and 24) to bond the die to the capacitor tape and to a plurality of leads (18). The tape also includes two conductive layers (26 and 28), made for instance of copper foil, which serve as the two electrodes of the capacitor. The electrodes are separated by a dielectric layer (30) which in one embodiment comprises barium-titanate (BaTiO.sub.3). The electrodes of the capacitor are electrically coupled to appropriate power and ground leads of the device by bonding wires (36 and 40) and to appropriate bonding pads (16) also by bonding wires (38 and 42). The bonding wires can be configured using any of three available wiring options. The present invention can also be implemented in a chip-on-lead (COL) device.

Abstract: A non-linear superconducting junction device comprising a layer of high transient temperature superconducting material which is superconducting at an operating temperature, a layer of metal in contact with the layer of high temperature superconducting material and which remains non-superconducting at the operating temperature, and a metal material which is superconducting at the operating temperature and which forms distributed Sharvin point contacts with the metal layer.

Abstract: A HEMT type semiconductor device includes a semiconductor substrate, a buffer semiconductor layer formed on the substrate, a first semiconductor well layer formed on the buffer layer and serving as a first conductivity type channel layer, a second semiconductor well layer formed on the first well layer and serving as a second conductivity type opposite the first conductivity, a channel layer and a potential barrier layer formed on the second well layer and forming a potential barrier for carriers. The substrate is made of GaAs or InP, and the layers are successively and epitaxially grown on the substrate. A two dimensional hole gas and a two dimensional electron gas are confined in the first well layer and in the second well layer, respectively.

Abstract: A method is provided for writing into a semiconductor memory which includes a MOS transistor formed on a semiconductor substrate and an anti-fuse formed of an insulating film and an upper electrode on a drain of the MOS transistor. The method includes the steps of applying a first voltage between the upper electrode of the anti-fuse and a source of the MOS transistor to cause dielectric breakdown of the insulating film of the anti-fuse, with the MOS transistor turned on; and applying a second voltage between the upper electrode of the anti-fuse and the semiconductor substrate so that a larger amount of current flows than the amount of current required for breaking down the insulating film of the anti-fuse.

Abstract: A gate insulating layer, which is formed on a channel region of a semiconductor substrate and interposed between the semiconductor substrate and a gate electrode, consists of a first part and a second part adjoining each other. The first part includes an oxide lower layer and a nitride upper layer, and a second part includes a nitride lower layer and an oxide upper layer.

Abstract: A compound semiconductor device and a process for manufacturing it is disclosed. The process comprises the steps of forming a first conduction type first clad layer, a first conduction type or second conduction type activated layer, a second conduction type second clad layer, and a second conduction type cap layer upon a first conduction type semiconductor substrate, forming a first conduction type electrode and a second conduction type electrode, and forming a rectangular pole shaped laser diode, a triangular pole shaped detecting photo-diode, and a triangular pole shaped receiving photo-diode by carrying out a single round of anisotropic etching. According to the present invention, the high density can be easily realized, so that the power consumption and the manufacturing cost can be saved.