Patents Examined by Alice W. Tang
  • Patent number: 5422513
    Abstract: A high density interconnect (HDI) structure having a dielectric multi-layer interconnect structure on a substrate is fabricated by forming a chip well, placing a chip in the well, and connecting the chip to the interconnect structure. Additionally, temperature sensitive chips or devices may be located beneath the dielectric multi-layer interconnect structure. A spacer die may be located in the substrate while the interconnect structure is fabricated and removed after a chip well aligned with the spacer die is formed, in order to accommodate a chip thickness which is greater than the dielectric multi-layer interconnect structure thickness.
    Type: Grant
    Filed: October 4, 1993
    Date of Patent: June 6, 1995
    Assignee: Martin Marietta Corporation
    Inventors: Walter M. Marcinkiewicz, Raymond A. Fillion, Barry S. Whitmore, Robert J. Wojnarowski
  • Patent number: 5422337
    Abstract: A Josephson junction device comprising a single crystalline substrate including a principal surface having two horizontal planes and a smooth slope between the two horizontal planes, and an oxide superconductor thin film formed on the principal surface of the substrate. The oxide superconductor thin film includes a first and a second superconducting portions of a single crystalline oxide superconductor respectively positioned on the two horizontal planes of the substrate, a junction portion of a single crystalline oxide superconductor having a different crystal orientation from the two superconducting portions positioned on the slope of the substrate and two grain boundaries between each of the two superconducting portions and the junction portion. The grain boundaries constitutes one weak link of the Josephson junction.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: June 6, 1995
    Assignee: Sumitomo Electric Industries
    Inventors: Saburo Tanaka, Takashi Matsuura, Hideo Itozaki
  • Patent number: 5420445
    Abstract: Only the areas of the CdTe/HgCdTe interface of a FPA detector circuit which is coupled by an epoxy to a silicon-based integrated circuit that require interdiffusing are heated to a sufficiently high temperature or have photons of light impinging thereon for a sufficient time to cause interdiffusion of the two layers by the travel of tellurium into the HgCdTe and the travel of mercury into the CdTe. The vast majority of the wafer is masked with an aluminum thin film to greatly reduce heat gain or photon transmission. An advantage of the process in accordance with the present invention is that only a very small fraction of the HgCdTe/epoxy/silicon-based integrated circuit wafer receives incoming energy during interdiffusion whereby problems caused by the differences in coefficient of thermal expansion between silicon and HgCdTe at the epoxy interface are minimized.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: May 30, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Michael F. Chisholm, David I. Forehand
  • Patent number: 5406123
    Abstract: Epitaxial growth of films on single crystal substrates having a lattice mismatch of at least 10% through domain matching is achieved by maintaining na.sub.1 within 5% of ma.sub.2, wherein a.sub.1 is the lattice constant of the substrate, a.sub.2 is the lattice constant of the epitaxial layer and n and m are integers. The epitaxial layer can be TiN and the substrate can be Si or GaAs. For instance, epitaxial TiN films having low resistivity can be provided on (100) silicon and (100) GaAs substrates using a pulsed laser deposition method. The TiN films were characterized using X-ray diffraction (XRD), Rutherford back scattering (RBS), four-point-probe ac resistivity, high resolution transmission electron microscopy (TEM) and scanning electron microscopy (SEM) techniques. Epitaxial relationship was found to be <100> TiN aligned with <100> Si. TiN films showed 10-20% channeling yield. In the plane, four unit cells of TiN match with three unit cells of silicon with less than 4.0% misfit.
    Type: Grant
    Filed: June 11, 1992
    Date of Patent: April 11, 1995
    Assignee: Engineering Research Ctr., North Carolina State Univ.
    Inventor: Jagdish Narayan
  • Patent number: 5401714
    Abstract: A field-effect structure formed on a substrate and comprising a channel with source and drain as well as a gate that is separated from the channel by an insulating layer. The channel is made of a high T.sub.c metal-oxide superconductor, e.g., YBaCuO, having a carrier density of about 10.sup.21 /cm.sup.3 and a correlation length of about 0.2 nm. The channel thickness is preferrable in the order of 1 nm. The superconductor is preferably a single crystalline and oriented such that the superconducting behavior is strongest in the plane parallel to the substrate. With a signal of a few volts applied to the gate, the entire channel cross-section is depleted of charge carriers whereby the channel resistance can be switched between a "zero resistance" (undepleted, superconducting) state and "very high resistance" (depleted state).
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: March 28, 1995
    Assignee: International Business Machines Corporation
    Inventors: Preveen Chaudhari, Carl A. Mueller, Hans P. Wolf
  • Patent number: 5396089
    Abstract: A unipolar electronic component is proposed with a quasi one dimensional carrier channel which has all the characteristics of an FET. This component can be very simply produced, has "self-alignment" and linear gates with a low capacity in place of planar gates. In this way a very high operating frequency of the component is possible. The structure comprises an initially homogenous 2D-layer with a high carrier mobility which is formed by epitaxy of for example GaAs. The implantation of focussed ions (for example Ga.sup.+ with 100 keV) locally destroys the conductivity of the electron layer. The irradiated regions remain insulating at low temperature or room temperature even after illuminating the cristal with bandgap radiation. The writing in of the insulating layer is carried out along two paths on the chip so that the 2D-carrier layer is subdivided into three regions insulated from one another.
    Type: Grant
    Filed: March 22, 1993
    Date of Patent: March 7, 1995
    Assignee: Max-Planck-Gesellschaft zur Forderung der Wissenschaften
    Inventors: Andreas D. Wieck, Klaus Ploog
  • Patent number: 5394004
    Abstract: A semiconductor device and a method of making the same capable of simplifying the process of making and reducing the cost of making. In the method a first layer is formed which has a plurality of conductors at its edge portion. Thereafter, a second layer is formed on the first layer which is to be selectively etched to form a pattern. During the etching, current is detected from the conductors and the etching is stopped dependent on the current detected from the conductors. The semiconductor device includes a transparent electrode on a substrate the transparent electrode having protrusions which have a top surface. A first insulation layer exists between the protrusions. There is a color emitting layer on the top surfaces of the protrusions and the insulation layer.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: February 28, 1995
    Assignee: Goldstar Co., Ltd.
    Inventor: Jae S. Jeong
  • Patent number: 5386139
    Abstract: A semiconductor light emitting element in which light leakage from the vicinity of an active layer end thereof is significantly reduced, and an interval at which the element is disposed is sufficiently narrow, so that there can be realized an optimal distance-measuring accuracy when used for a light source of a camera's automatic focusing mechanism.
    Type: Grant
    Filed: April 15, 1993
    Date of Patent: January 31, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Idei, Toshio Shimizu
  • Patent number: 5384483
    Abstract: A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit.
    Type: Grant
    Filed: February 28, 1992
    Date of Patent: January 24, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Kuei-Wu Huang
  • Patent number: 5382813
    Abstract: A light emission diode comprises a semiconductor substrate and a pn junction structure including an n-type ZnS compound semiconductor layer and a p-type ZnS compound semiconductor layer, Al being present in at least one of the semiconductor layers. By this, the diode is able to emit blue light at a high luminous intensity.
    Type: Grant
    Filed: November 9, 1993
    Date of Patent: January 17, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yoshio Morita
  • Patent number: 5378926
    Abstract: A gallium arsenide monolithic microwave integrated circuit (MMIC) chip (12) has microelectronic devices (16, 18) formed on a frontside surface (12a), and via holes (12c, 12d) formed through the chip (12) from the frontside surface (12a) to a backside surface (12b). The backside surface (12b) of the chip (12) is bonded to a molybdenum carrier (14) by an eutectic gold/tin alloy (20). A barrier layer (22) including a refractory metal nitride material (22a) is sputtered onto the backside surface (12b) and into the via holes (12c, 12d) of the chip (12) prior to bonding. The barrier layer (22) blocks migration of tin from the eutectic gold-tin alloy (20) through the via holes (12c,-12d) to the frontside surface (12a) of the chip (12) during the bonding operation, thereby preventing migrated tin from adversely affecting the microelectronic devices (16, 18).
    Type: Grant
    Filed: January 10, 1994
    Date of Patent: January 3, 1995
    Assignee: Hughes Aircraft Company
    Inventors: Tom Y. Chi, Brook D. Raymond
  • Patent number: 5378683
    Abstract: The disclosure relates to a Josephson junction formed by a non-superconducting barrier between two superconducting films of the (R) BaCuO (R=rare earth) group. In order to take advantage of the greater coherence length of superconductors along the CuO planes, i.e. perpendicularly to the long axis "c" of the crystal unit cell, the superconducting film is oriented so that the axis "c" is parallel to the plane of the junction. The device can be applied to Josephson junctions and to SQUIDs.
    Type: Grant
    Filed: April 21, 1992
    Date of Patent: January 3, 1995
    Assignee: Thomson-CSF
    Inventors: Regis Cabanel, Guy Garry, Alain Schuhl, Bruno Ghyselen
  • Patent number: 5378905
    Abstract: There is interposed a buffer film composed of IIa group fluoride and having characteristics of orientation to a surface direction (111), in which mismatching in lattice constant with a crystal element of a semiconductor substrate is large and mismatching in lattice constant with IV-VI group compound ferroelectric substance is small, between the semiconductor substrate having a surface direction (100) and a ferroelectric gate film comprising the IV-VI group compound ferroelectric substance and having characteristics of polarization to the surface direction (111). Since the buffer film is an orientation film in the direction of (111) without influenced by a crystal element of the semiconductor substrate serving as a base material, the ferroelectric gate film can be oriented in the direction of (111) which is the same as the direction of polarization of the ferroelectric substance.
    Type: Grant
    Filed: February 18, 1993
    Date of Patent: January 3, 1995
    Assignee: Rohm Co., Ltd.
    Inventor: Takashi Nakamura
  • Patent number: 5376626
    Abstract: A superconducting switch is composed of anisotropic magnetic material. The switch has a first superconducting section, a variable resistive section and a second superconducting section. An external magnetic field is applied so that the first and second superconducting sections remain superconducting and the resistive section changes resistance when the magnetic field applied exceeds the critical field of the variable resistance section. The different critical field regions are achieved by exploiting the natural critical field anisotropy of the ceramic superconductors (a previously unobserved phenomena in metal superconductors). By making the different sections with different orientations they will exhibit different critical field valves for a given direction of applied fields. The state of the switch is changed by either increasing or decreasing the external magnetic field about the critical field value of the resistive section of the switch.
    Type: Grant
    Filed: October 2, 1992
    Date of Patent: December 27, 1994
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Alvin J. Drehman, Stephen Bachowski
  • Patent number: 5376624
    Abstract: A Josephson break junction device suitable for highly sensitive electronic detecting systems. A superconductor film such as YBa.sub.2 Al.sub.3 O.sub.7 is deposited on a substrate such as a single-crystal MgO. The film is fractured across a narrow strip by at least one indentation in the substrate juxtaposed from the strip to form a break junction. A transducer is affixed to the substrate for applying a bending movement to the substrate to regulate the distance across the gap formed at the fracture to produce a Josephson turned junction effect. Alternatively, or in addition to the transducer, a bridge of a nobel metal is applied across the gap to produce a weak-link junction.
    Type: Grant
    Filed: October 10, 1991
    Date of Patent: December 27, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Ignacio M. Perez, William R. Scott
  • Patent number: 5374472
    Abstract: A ferromagnetic .delta.-Mn.sub.1-x Ga.sub.x thin film having perpendicular anisotropy is described which comprises: (a) a GaAs substrate, (b) a layer of undoped GaAs overlying said substrate and bonded thereto having a thickness ranging from about 50 to about 100 nanometers, (c) a layer of .delta.-Mn.sub.1-x Ga.sub.x overlying said layer of undoped GaAs and bonded thereto having a thickness ranging from about 20 to about 30 nanometers, and (d) a layer of GaAs overlying said layer of .delta.-Mn.sub.1-x Ga.sub.x and bonded thereto having a thickness ranging from about 2 to about 5 nanometers, wherein x is 0.4 .+-.0.05.
    Type: Grant
    Filed: January 4, 1994
    Date of Patent: December 20, 1994
    Assignee: The Regents, University of California
    Inventor: Kannan M. Krishnan
  • Patent number: 5367189
    Abstract: A semiconductor device comprises a first electrode buried in one main face of a substrate and surrounded by a first insulator, a field oxide film covering the surface of the first electrode, a semiconductor layer connected with the first electrode, a second insulator covering the surface of the semiconductor layer, a second electrode connected with the semiconductor layer, a gate electrode connected with the semiconductor layer between the second insulator and the field oxide film, and an outgoing electrode connected with the first electrode.
    Type: Grant
    Filed: November 4, 1992
    Date of Patent: November 22, 1994
    Assignee: Fujitsu Limited
    Inventor: Shunji Nakamura
  • Patent number: 5362709
    Abstract: A superconducting tunnel junction is disclosed herein. The superconducting tunnel junction is characterized in that a pair of oxide superconducting layers thereof and a tunnel barrier layer located between the oxide superconducting layers have the same or almost the same crystal structure and the same or almost the same lattice constant in a direction of a, b, or c axis. The layers have good crystallization.
    Type: Grant
    Filed: October 22, 1991
    Date of Patent: November 8, 1994
    Assignee: Semiconductor Energy Laboratory, Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 5360982
    Abstract: Optoelectronic semiconductor devices which have a groove-shaped waveguide in an oxide layer provided on a silicon substrate are compact, easy to manufacture, and--when the waveguide comprises a non-linear optical material--applicable inter alia for frequency doubling of laser radiation. In known devices, scattering losses occur in the waveguide owing to the roughness of the groove which arises during etching of the groove. Here, the groove and a portion of the oxide layer are formed by local, preferably thermal, oxidation of the silicon substrate. The groove formed at the area of the oxidation mask has a smoother surface and as a result the waveguide has lower losses. When the device includes a GaAs/AlGaAs diode laser, it forms an efficient, compact, inexpensive and blue-emitting laser source which is suitable for use in an optical disc system. Preferably, the diode laser is situated in a deeper and wider further groove in the oxide layer.
    Type: Grant
    Filed: December 1, 1993
    Date of Patent: November 1, 1994
    Assignee: U.S. Philips Corporation
    Inventor: Antonius H. J. Venhuizen
  • Patent number: 5358925
    Abstract: An HTSC material epitaxially deposited on a YSZ buffer layer on a surface of a monocrystalline silicon substrate has a zero resistance transition temperature of at least 85.degree. K., a transition width (10-90%) of no more than 1.0.degree. K., a resistivity at 300.degree. K. of no more than 300 micro-ohms-centimeter and a resistivity ratio (at 300.degree. K./100.degree. K.) of 3.0.+-. 0.2. The surface of the silicon substrate is cleaned using a spin-etch process to produce an atomically clean surface terminated with an atomic layer of an element such as hydrogen with does not react with silicon. The substrate can be moved to a deposition chamber without contamination. The hydrogen is evaporated in the chamber, and then YSZ is epitaxially deposited preferably by laser ablation. Thereafter, the HTSC material, such as YBCO, is epitaxially deposited preferably by laser ablation. The structure is then cooled in an atmosphere of oxygen.
    Type: Grant
    Filed: August 10, 1992
    Date of Patent: October 25, 1994
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventors: George A. Neville Connell, David B. Fenner, James B. Boyce, David K. Fork