Patents Examined by Allan Olsen
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Patent number: 9054050Abstract: Techniques disclosed herein include methods for etching deep silicon features using a continuous gas pulsing process that etches high aspect ratio features having a relatively smooth profile. Such methods provide an etch rate faster than time-multiplexed etch-deposition processes. Techniques include using a continuous process that comprises a cyclic gas-pulsing process of alternating chemistries. One process gas mixture includes a halogen-containing silicon gas and oxygen that creates an oxide layer. A second process gas mixture includes a halogen-containing gas and a fluorocarbon gas that etches oxide and silicon.Type: GrantFiled: November 6, 2013Date of Patent: June 9, 2015Assignee: Tokyo Electron LimitedInventors: Scott W. LeFevre, Alok Ranjan
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Patent number: 9039910Abstract: The present invention provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a microwave power generator coupled to the to the chamber body through a waveguild, and one or more coils or magnets disposed around an outer circumference of the chamber body adjacent to the waveguide, and a gas source coupled to the waveguide through a gas delivery passageway.Type: GrantFiled: October 19, 2011Date of Patent: May 26, 2015Assignee: APPLIED MATERIALS, INC.Inventors: Banqiu Wu, Ajay Kumar
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Patent number: 9034770Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch created from a remote plasma etch. The remote plasma excites a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. Reactants thereby produced etch the patterned heterogeneous structures to remove two separate regions of differing silicon oxide at different etch rates. The methods may be used to remove low density silicon oxide while removing less high density silicon oxide.Type: GrantFiled: March 15, 2013Date of Patent: May 19, 2015Assignee: Applied Materials, Inc.Inventors: Seung H. Park, Yunyu Wang, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
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Patent number: 9034141Abstract: A thin film forming apparatus and a thin film forming method using the same are disclosed. In one aspect, the thin film forming apparatus comprises a mask that includes a blocking portion and an opening. It also includes an etching source that jets an etching gas through the opening of the mask to etch a thin film according to a pattern. The mask includes a gas blower for blowing a gas around the opening so that the etching gas does not penetrate into a thin film area corresponding to the block portion. When the thin film forming apparatus is used, a normal residual area of a thin film may be safely preserved and patterning may be accurately performed. Thus, the quality of a product manufactured by using the thin film forming apparatus may be improved.Type: GrantFiled: May 30, 2013Date of Patent: May 19, 2015Assignee: Samsung Display Co., Ltd.Inventors: Sung-Joong Joo, You-Min Cha
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Patent number: 9023225Abstract: A pattern forming method includes forming a pattern forming material film on a substrate as an etching target film, the pattern forming material film having an exposing section that has porosity upon exposure and a non-exposing section, patterning and exposing the pattern forming material film for the exposing section to have the porosity, selectively infiltrating a filling material into voids of the exposing section to reinforce the exposing section, and removing the non-exposing section of the pattern forming material film by dry etching to form a predetermined pattern.Type: GrantFiled: September 26, 2013Date of Patent: May 5, 2015Assignee: Tokyo Electron LimitedInventors: Kenichi Oyama, Hidetami Yaegashi
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Patent number: 9011631Abstract: An inductively coupled plasma processing apparatus includes a processing chamber in which a semiconductor substrate is processed, a substrate support, a dielectric window forming a wall of the chamber, an antenna operable to generate and maintain a plasma in the processing chamber, and a showerhead plate of dielectric material adjacent the dielectric window. The showerhead plate includes gas holes in fluid communication with a plenum below the dielectric window, the plenum having a gas volume of no greater than 500 cm3. The gas holes extend between the plenum and a plasma exposed surface of the showerhead plate and the gas holes have an aspect ratio of at least 2. A gas delivery system is operable to supply an etching gas and a deposition gas into the processing chamber through the showerhead plate while the semiconductor substrate is supported on the substrate support.Type: GrantFiled: February 2, 2012Date of Patent: April 21, 2015Assignee: Lam Research CorporationInventor: Theo Panagopoulos
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Patent number: 9011703Abstract: A method for manufacturing a touch screen panel includes forming first and second conductive layers on a substrate, forming a photosensitive layer on the second conductive layer, exposing the photosensitive layer using a first mask having a first light shielding pattern that corresponds to sensing electrodes and lines to be formed, removing the photosensitive layer at the first exposed portion, sequentially removing the second and first conductive layers at the first exposed portion using the first remaining photosensitive layer as a mask, exposing the photosensitive layer using a second mask having a second light shielding pattern that corresponds to the lines to be formed, removing the photosensitive layer at the second exposed portion, removing the second conductive layer at the second exposed portion using the second remaining photosensitive layer as a mask, thereby forming the sensing electrodes and the lines, and removing the second remaining photosensitive layer.Type: GrantFiled: April 16, 2013Date of Patent: April 21, 2015Assignee: Samsung Display Co., Ltd.Inventor: Sang-Min Baek
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Patent number: 9005473Abstract: A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising a substrate and the silicon oxide to an ammonium fluoride chemical treatment and a subsequent plasma treatment, both of which may be effected in the same vacuum chamber of a processing apparatus. The ammonium fluoride chemical treatment converts the silicon oxide to a solid reaction product in a self-limiting reaction, the solid reaction product then being volatilized by the plasma treatment. The plasma treatment includes a plasma having an ion bombardment energy of less than or equal to approximately 20 eV. An ammonium fluoride chemical treatment including an alkylated ammonia derivative and hydrogen fluoride is also disclosed.Type: GrantFiled: August 9, 2012Date of Patent: April 14, 2015Assignee: Micron Technology, Inc.Inventors: Mark W. Kiehlbauch, J. Neil Greeley, Paul A. Morgan
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Patent number: 9005460Abstract: The present invention provides methods of selectively removing one or more graphene layers from a graphene material by: (1) applying a metal to a surface of the graphene material; and (2) applying a hydrogen containing solution to the surface of the graphene material that is associated with the metal. The hydrogen containing solution dissolves the metal along with one or more layers of graphene associated with the metal, thereby removing the layer(s) of graphene from the graphene material. In some embodiments, the hydrogen containing solution is an acidic solution, such as hydrochloric acid. In some embodiments, the metal is zinc. In some embodiments, the methods of the present invention are utilized to selectively remove one or more layers of graphene from one or more targeted sites on the surface of a graphene material.Type: GrantFiled: October 11, 2011Date of Patent: April 14, 2015Assignee: William Marsh Rice UniversityInventors: James M. Tour, Ayrat M. Dimiev, Dmitry V. Kosynkin
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Patent number: 9006106Abstract: Methods of removing metal hardmasks in the presence of ultra low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film includes forming a pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. The method also includes etching, using the metal nitride hardmask layer as a mask, the pattern at least partially into the low-k dielectric film, the etching involving using a plasma etch based on SiFx. The etching also involves forming an SiOx passivation layer at least on sidewalls of the low-k dielectric film formed during the etching. The method also includes removing the metal nitride hardmask layer by a dry etch process, where the SiOx passivation layer protects the low-k dielectric film during the removing.Type: GrantFiled: May 8, 2013Date of Patent: April 14, 2015Assignee: Applied Materials, Inc.Inventors: Chia-Ling Kao, Kwang-soo Kim, Sean S. Kang, Srinivas D. Nemani
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Patent number: 9005459Abstract: A disclosed film deposition method includes steps of loading plural substrates each of which includes a pattern including a concave part in a reaction chamber in the form of shelves; depositing a silicon oxide film on the plural substrates by supplying a silicon-containing gas and an oxygen-containing gas to the reaction chamber; etching the silicon oxide film deposited on the plural substrates in the step of depositing by supplying a fluorine-containing gas and an ammonia gas to the reaction chamber; and alternately repeating the step of depositing and the step of etching.Type: GrantFiled: March 15, 2012Date of Patent: April 14, 2015Assignee: Tokyo Electron LimitedInventors: Akinobu Kakimoto, Satoshi Takagi, Toshiyuki Ikeuchi, Katsuhiko Komori, Kazuhide Hasebe
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Patent number: 8999849Abstract: A semiconductor is fabricated on a silicon (Si) substrate. The semiconductor is III-nitride based. The Si substrate is partially isolated. Etching is directly processed from top on a chip for solving wire-width problem. The Si substrate does not need to be made thin. The chip can be large scaled and be prevented from bowing. Thus, the present invention simplifies producing procedure and reduces production cost. Besides, for a large-scaled chip, the breakdown voltage is enhanced; and, without making the Si substrate thin, the on-state current is remained the same and the heat problem is weakened.Type: GrantFiled: December 2, 2013Date of Patent: April 7, 2015Assignee: National Tsing Hua UniversityInventors: Yu-Syuan Lin, Shuo-Hung Hsu, Yi-Wei Lien
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Patent number: 8999193Abstract: Chemical-mechanical polishing (CMP) compositions containing chemical additives and methods of using the CMP compositions are disclosed. The CMP composition comprises abrasive; chemical additive; liquid carrier; optionally an oxidizing agent; a pH buffering agent and salt; a surfactant and a biocide. The CMP compositions and the methods provide enhanced removing rate for “SiC”, SiN” and “SiCxNy” films; and tunable removal selectivity for “SiC” in reference to SiO2, “SiN” in reference to SiO2, “SiC” in reference to “SiN”, or “SiCxNy” in reference to SiO2; wherein x ranges from 0.1 wt % to 55 wt %, y ranges from 0.1 wt % to 32 wt %.Type: GrantFiled: March 15, 2013Date of Patent: April 7, 2015Assignee: Air Products and Chemicals, Inc.Inventors: Xiaobo Shi, James Allen Schlueter, Maitland Gary Graham, Savka I. Stoeva, James Matthew Henry
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Patent number: 8999181Abstract: In a method for manufacturing a ridge-type waveguide, a substrate is provided. An etching resistance stripe is coated on the substrate. The substrate with the etching resistance stripe is subjected to a wet etching process to form a ridge under the etching resistance stripe. The etching resistance stripe is removed. A titanium stripe is then coated onto the ridge and diffused into the ridge to form a waveguide in the ridge by a high temperature diffusing process.Type: GrantFiled: May 30, 2013Date of Patent: April 7, 2015Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Hsin-Shun Huang
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Patent number: 8999177Abstract: Out-of-plane microneedle manufacturing process comprising the simultaneous creation of a network of microneedles and the creation of a polygonal shaped hat (2) above each microneedle (1) under formation, said process comprising the following steps: providing bridges (3) between the hats (3), maintaining the bridges (3) during the remaining microneedle manufacturing steps, removing the bridges (3), together with the hats (2), when the microneedles (1) are formed.Type: GrantFiled: October 17, 2008Date of Patent: April 7, 2015Assignee: Debiotech S.A.Inventors: Astrid Cachemaille, Francois Cannehan
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Patent number: 8992790Abstract: A patterning process which uses self-assembly, including: forming a silicon-containing film by applying a silicon-containing film composition having an organic substituent group substituted with an acid labile group onto a substrate to be processed, forming a photoresist film onto the silicon-containing film, pattern-exposing of the photoresist film, removing the photoresist film, forming a polymer film by applying a self-assembling polymer onto the silicon-containing film, self-assembling the polymer film to form a microdomain structure, forming a pattern of the polymer film having the microdomain formed, transferring the pattern to the silicon-containing film by using the pattern formed on the polymer as a mask, and transferring the pattern to the substrate to be processed by using the pattern transferred to the silicon-containing film as a mask. There can be provided a pattern having a microdomain structure formed by self-assembly with uniformity and regularity.Type: GrantFiled: April 15, 2013Date of Patent: March 31, 2015Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Tsutomu Ogihara, Jun Hatakeyama
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Patent number: 8993451Abstract: Etch stabilizing ions (37) are introduced, e.g., by ion implantation (34), into a portion (36) of a substrate (20) underlying an etch window (24) in a masking layer (22) covering the substrate (20), where a trench (26) is desired to be formed. When the portion (36) of the substrate (20) containing the etch stabilizing ions (37) is etched to form the trench (26), the etch stabilizing ions (37) are progressively released at the etch interface (28?) as etching proceeds, substantially preventing gas micro-bubbles or other reaction products at the etch interface (28?) from disrupting etching. Using this method (700), products containing trenches (26) are much more easily formed and such trenches (26) have much smoother interior surface (28).Type: GrantFiled: April 15, 2011Date of Patent: March 31, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Srivatsa G. Kundalgurki, James F. McHugh
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Patent number: 8980113Abstract: A method for chemical mechanical polishing of a substrate includes polishing the substrate at a stock removal rate of greater than about 2.5 ?/min to achieve a Ra of not greater than about 5.0 ?. The substrate can be a III-V substrate or a SiC substrate. The polishing utilizes a chemical mechanical polishing slurry comprising ultra-dispersed diamonds and at least 80 wt % water.Type: GrantFiled: March 12, 2010Date of Patent: March 17, 2015Assignee: Saint-Gobain Ceramics & Plastics, Inc.Inventors: Jun Wang, Ronald W. Laconto, Andrew G. Haerle
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Patent number: 8980048Abstract: A plasma etching apparatus includes a process chamber, a susceptor, microwave permeable plate that is made of a dielectric material that allows microwaves to pass therethrough, a microwave supplying portion including a microwave generation apparatus that generates microwaves of a predetermined frequency, a gas supplying portion for supplying a process gas, an evacuation portion, a bias electric power supplying portion; and an alternating bias electric power control portion that controls the alternating bias electric power, wherein the alternating bias electric power control portion controls the alternating bias electric power so that supplying and disconnecting the alternating bias electric power to the susceptor are repeated to allow a ratio of a time period of supplying the alternating bias electric power with respect to a total time period of supplying the alternating bias electric power and disconnecting the alternating bias electric power to be 0.1 or more and 0.5 or less.Type: GrantFiled: April 30, 2014Date of Patent: March 17, 2015Assignee: Tokyo Electron LimitedInventors: Tetsuya Nishizuka, Masahiko Takahashi, Toshihisa Ozu
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Patent number: 8969210Abstract: There is provided a plasma etching apparatus provided for performing an etching in a desirable shape. The plasma etching apparatus includes a processing chamber 12 for performing a plasma process on a target substrate W; a gas supply unit 13 for supplying a plasma processing gas into the processing chamber 12; a supporting table positioned within the processing chamber 12 and configured to support the target substrate thereon; a microwave generator 15 for generating a microwave for plasma excitation; a plasma generation unit for generating plasma within the processing chamber 12 by using the generated microwave; a pressure control unit for controlling a pressure within the processing chamber 12; a bias power supply unit for supplying AC bias power to the supporting table 14; and a control unit for controlling the AC bias power by alternately repeating supply and stop of the AC bias power.Type: GrantFiled: September 14, 2011Date of Patent: March 3, 2015Assignee: Tokyo Electron LimitedInventors: Toshihisa Nozawa, Masaru Sasaki, Jun Hashimoto, Shota Yoshimura, Toshihisa Ozu, Tetsuya Nishizuka