Abstract: The present invention relates to a parallel processor system that can reduce the hardware circuit amount of the portions except a memory capacity. In the parallel processor system, each S-DPr (Source Data Processor) executes a local leveling process to level equally all loads to T-DPrs (Target Data Processor) related to data sent from itself so that the leveling is performed to all the T-DPrs and the chunks as a whole. The parallel processor system is applicable to super-database computers that perform the MIMD-type process.

Abstract: An apparatus and methods are provided for pre-compressing data to be sent to a peripheral device in a computer system, sending the data to the peripheral device as a compressed data stream, and decompressing the data for use in the peripheral device in a real-time format. In a preferred embodiment, a unique peripheral device controller is provided having a data handling and decompression pipeline for receiving and decompressing an incoming compressed data stream in concert with a state machine for sensing the states of elements of the peripheral device, and for providing the decompressed data stream to data-using elements of the peripheral device. The peripheral device can be any device for which large amounts of data are typically needed, including, but not limited to printers, video displays, robotic driving devices, and data recording and media writing devices. Alternative methods are disclosed for compressing and decompressing data in systems according to the invention.

Abstract: Method, system, and apparatus are described for automatically receiving, at an intermediate processing location, data from a wide variety of remote sources, identifying the format of the data, translating the data to a common file format, sending the data to a recipient in an intermediate format, then translating the data to the specific format needed by the particular recipient. The system operates automatically with little human intervention. A unique system for automatically selecting and implementing specific translation modules is also described. Error checking features ensure that the transferred data matches the original data although the format is altered, and documentary receipts are sent to each section of the system that sends data, and logical, statistical and mathematical operations may be performed on the data.

Abstract: An apparatus and methods are provided for pre-compressing data to be sent to a peripheral device in a computer system, sending the data to the peripheral device as a compressed data stream, and decompressing the data for use in the peripheral device in a real-time format. In a preferred embodiment, a unique peripheral device controller is provided having a data handling and decompression pipeline for receiving and decompressing an incoming compressed data stream in concert with a state machine for sensing the states of elements of the peripheral device, and for providing the decompressed data stream to data-using elements of the peripheral device. The peripheral device can be any device for which large amounts of data are typically needed, including, but not limited to printers, video displays, robotic driving devices, and data recording and media writing devices. Alternative methods are disclosed for compressing and decompressing data in systems according to the invention.

Abstract: A data arrangement for an apparatus connectable to a communication network comprises data points (6.1..6.n) arranged in an apparatus and also a characterization of the apparatus. In a data point 6.k, with an index k of 1 to n, dynamic process information is storable. With apparatus connected, the data points (6.1..6.n) are accessible over the communication network for a station connected to the communication network for the reading and/or changing, in which also a single data point (6.k) is accessible. The characterization is a static description of objects of the apparatus in which a single data point (6.k) or also a group of data points (6.k) are objects of the apparatus. The data arrangement creates the precondition that in the operation of the apparatus an access is feasible to a data point (6.k) with a minimum of data traffic on the data network. The available characterization makes possible, further, a data-controlled realization of a user program.

Abstract: Methods and test platforms for developing an application-specific integrated circuit incorporating, on the same chip, a signal processor core, RAM memory and ROM memory intended to receive a management program and processing program, and input-output management peripherals specific to the application. The signal processor, RAM memory and ROM memory correspond respectively to existing separate IC components. The processing program is developed and tested on a test platform including at least these separate IC components together with a core-emulation integrated circuit, which includes the signal processor core in a minimal configuration. An interface program and diagnostic interface logic allows the platform to be controlled from a microcomputer, which can thereby implement automatic chaining of tests.

Abstract: A dual-directional parallel processor. The inventive processor (10) includes an array (20) of processing elements (30). Each processing element has a first circuit (31) for inputting and outputting data, a second circuit (32) for inputting and outputting data; and a third circuit (33, 34) for setting the first circuit (31) in an input mode and for setting the second circuit (32) in an output mode in response to a first mode control signal. The third circuit (33, 34) also sets the first circuit (31) in an output mode and the second circuit (32) in an input mode in response to a second mode control signal. In the illustrative embodiment, data is communicated between the first and the second circuits (31, 32) and the processor further includes a fifth circuit (12) for inputting data to the array and a sixth circuit (14) for outputting data from the array.

Abstract: A computer apparatus for receiving a removable communication card such as a radio card or a modem card. A radio or modem is serf-contained inside a housing of the communication card and has an electrical interface for communicating information to and from the computer apparatus. The computer apparatus receives the communication card such that it engages the electrical interface. These contacts automatically connect the communication card to an appropriate antenna, telephone or telephone line. A radio communication card is connected to the appropriate antenna for the type and frequency of the radio. A modem card is connected to a standard telephone line, a cellular phone, or an antenna for a cellular phone if the cellular phone is also disposed within the housing of the modem communication card. Additionally, a switching matrix can be used to connect one set of contacts on a radio card or a modem card to one or more of a plurality of antennas and telephone lines.

Abstract: A method and apparatus for providing bus protocol simulation in a multi-processor data processing system (10). A plurality of edge interface circuits (14,16) are used to interface a first bus (32, 34, 36), which uses a first bus protocol, with a plurality of data processors (50-65), each of which uses a second bus protocol. A memory (90) within each edge interface circuit (14,16) is loaded with a plurality of values. Each of the plurality of values has a control portion and a data portion. The control portion of memory entry "N" is used to initiate the transfer of the data from memory entry "N+1". In an alternate embodiment, multi-processor data processing system (210) includes a plurality of data processors (250-258) and a plurality of edge interface circuits (214-217).

Abstract: A microcomputer whose ROM program can be altered without the necessity of rebuilding or remaking the ROM, wherein when an address outputted from a CPU to an address bus matches one of the addresses of locations at which the ROM program is to be altered, the ROM is disconnected from a data bus and a jump instruction op code is outputted to the data bus, followed by the start address of an altered contents stored in a RAM or the start address of an instruction for locating among a plurality of altered contents, the start address of the altered content that is substituted for the portion of the program to be altered; then, the CPU reads the jump instruction op code and the start address, the operand of the jump instruction, outputted on the data bus, and executes the jump instruction by which a jump occurs from the ROM program to the altered contents stored in the RAM to execute the altered contents, and control returns to the ROM program after the execution of each altered content, thereby altering the ROM prog

Abstract: A system and method for preprocessing and delivering multimedia presentations to customers such that delays due to interactive response time is virtually eliminated include a preprocessor, mass storage, a delivery processor, a distribution network, and a plurality of presentation processors. The preprocessor receives as inputs an original multimedia presentation and parameters characterizing other system components, which parameters include the round trip latency between the delivery processor and a presentation processor, and generates a preprocessed multimedia presentation including a delivery schedule in the form of a labelled, directed graph.

Abstract: A computer processor for performing mathematical operations includes a logarithm converter which generates log values on a data bus, a plurality of processing elements connected to the data bus, an inverse-logarithm converter which receives values from the processing elements, an accumulator which sums converted values from the inverse-logarithm converter, and a control unit for configuring the accumulator to perform various summing operations. The computer processor also includes a switch for providing processor outputs as feedback. An instruction, selected from a set of instructions, is decoded by the control unit to configure the computer processor to perform operations on a data stream.

Abstract: The methods concern fully utilizing storage capacity in a heterogenous hierarchic disk array having storage disks of differing capacities. The disks are segmented into multiple regions. One method links non-contiguous regions from individual storage disks to form RAID areas. The RAID areas are mapped into a virtual storage space that provides a view of the physical storage space as a single storage volume. Data is then stored in these RAID areas according to different redundancy criteria, such as RAID Level 1 and RAID Level 5. A second method fully utilizes of storage capacity by configuring the heterogeneous disk array to employ a minimum of two equal-sized storage disks that have larger capacity than other individual storage disks in the disk array. The contiguous regions across the multiple disks are then grouped together to form the RAID areas.

Abstract: A method and apparatus for interfacing multiple integrated circuit chip devices to a system bus includes higher speed portions of a circuit within a primary IC chip and lower speed portions of a circuit within a secondary IC chip. The primary IC chip connects directly to the system bus while the secondary IC chip receives the same bus signals via the primary IC chip after a one clock cycle delay. Both the primary and secondary IC chips are capable of driving signals out onto the system bus when the primary and secondary ICs are part of a bus master circuit. When the primary and secondary ICs act as bus masters, signals are received by the secondary IC chip in the same clock cycle as the primary IC chip receives the signals. Thus, the secondary IC includes a state machine to indicate if the received signals are delayed by one clock cycle or not. In a preferred embodiment, the same pins are used by the primary IC to drive signals through to the secondary IC as to drive signals out onto the system bus.

Abstract: A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

Abstract: A digital signal processing system includes a first and second memory coupled to first and second register banks respectively. The system further includes first and second multipliers coupled to the first and second register banks for producing first and second product outputs respectively. The system also includes an arithmetic logic unit having first, second and third inputs and an output. The first input is coupled to the first product output and the second and third inputs are selectively coupled to either of the second product output and the first and second register means. The arithmetic logic unit output is coupled to the first and second register banks for accumulating the sample values in the first and second register banks. The system further includes Instruction control for storing a plurality of instruction op codes and controlling the system to compute the sample values by performing simplex operations during each cycle of a plurality of operating cycles of a digital signal processing procedure.

Abstract: A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.

Abstract: A local area network switch includes a set of input ports each receiving and storing incoming packets from a corresponding network station, a set of output ports each forwarding packets to a corresponding network station, and a switching system for routing packets from the input ports to the output ports. The output ports are interconnected to form an output token passing ring and the input ports are interconnected to form an input token passing ring. Whenever an idle output port receives the output token, it holds the output token and signals the input ports to start an input token passing cycle. During an input token passing cycle, an input port storing a packet destined for an output token holder terminates the input token passing cycle when it receives the input token and signals the switching system to establish a connection to the output token holder. To fairly distribute arbitration priority, input and output ports starting positions are rotated for successive input and output token passing cycles.

Abstract: Discovery/layout software configures a general purpose computer system to act as a management station using an industry standard SNMP protocol. The discovery/layout software has a discovery mechanism and a layout mechanism which, in combination, permit the discovery/layout software to provide various submaps to a display for illustrating network topology, which includes devices and device interconnections of the network. The submaps correspond to various hierarchical views of the network. Significantly, a persistence specification mechanism is provided in the discovery/layout software for specifying a submap as either transient (generated upon demand) or persistent (exists whether demanded or not). An integrating application as well as the user can identify a submap as persistent. This feature enables better interfacing of the integrating application with the station, thereby providing more information to the user.

Abstract: A computer system which includes a page mode memory in which a particular piece of data is accessed by first supplying a page or row address, then supplying a column address. These addresses are input to the memory by row address strobe (RAS) signals and column address strobe (CAS) signals. The RAS signals are determined by comparing input CPU addresses with row starting address information stored in registers, each of which corresponds to a memory socket in which a memory module may be installed. An algorithm is described for initializing the memory and its memory controller, including a determination of the starting address information.