Abstract: A device which includes a substrate having a device region is provided. The device region may be a high voltage device region. A source region and a drain region are disposed in the substrate within the device region. A gate is arranged over the substrate and between the source region and the drain region. A trench structure having a trench is disposed in the substrate within the device region. The trench structure is arranged on a first side of the gate where a predetermined distance is arranged between the trench structure and the first side of the gate. A well tap region is disposed adjacent to the source region. The well tap region is arranged at least around a bottom and a sidewall of the trench. The well tap region has a deeper depth within the substrate as compared to the source region.

Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.

Abstract: The present invention provides an OLED display device, comprising: an OLED display panel, the OLED display panel comprising a display area and non-display areas in the both-ends edges of the display area; a dam unit and a film packaging layer. A part of the film packaging layer corresponding to the display area is disposed on the surface of the OLED display panel; another part of the film packaging layer corresponding to the non-display area is disposed on the surface of the dam unit; wherein, the dam unit comprises a flattening layer, a pixel isolation layer and a pixel support layer stacked-up together.

Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.

Abstract: Semiconductor structures are provided. Each of the transistors includes a first source/drain region over a semiconductor fin extending in a first direction, a second source/drain region over the semiconductor fin, a channel region in the semiconductor fin and between the first and second source/drain regions, and a metal gate electrode formed on the channel region and extending in a second direction perpendicular to the first direction. In a first transistor of the transistors, a first source/drain region is formed between the metal gate electrode of the first transistor and the metal gate electrode of a second transistor of the transistors, A second source/drain region is formed between the metal gate electrode of the first transistor and the dielectric-base dummy gate extending in the second direction. A first contact of the first source/drain region is narrower than a second contact of the second source/drain region along the first direction.

Abstract: The present invention teaches a TFT substrate manufacturing method and a TFT substrate. The method configures contact region vias in the source/drain contact regions at two ends of the active layer, provides buffer layer troughs in the buffer layer beneath the contact region vias, and forms undercut structure between the buffer layer troughs and the active layer around the contact region vias, thereby separating the transparent conductive layer at the contact region vias, and extending the source/drain electrodes to contact the source/drain contact regions of the active layer from below through the buffer layer troughs. The present invention therefore prevents the occurrence of Schottky contact barrier resulted from the contact between poly-Si and ITO in the 7-mask process by letting the source/drain electrodes to directly contact and form ohmic contact with the source/drain contact regions of the active layer, thereby enhancing the electronic mobility of TFT devices.

Abstract: Predicting maintenance needs and analyzing preventative maintenance requirements in electrically powered turbomachinery with multi-parameter sensors and power quality sensors, both of the Fog-type, providing time domain output data and transforming data samples into the frequency domain to detect a root cause of failure of the machinery.

Abstract: An electroluminescence display device includes: a first substrate and a second substrate facing each other, a bank configured to define a plurality of emission areas on the first substrate, a light-emitting layer including: a first light-emitting layer in a first emission area among the plurality of emission areas, a second light-emitting layer in a second emission area among the plurality of emission areas, and a third light-emitting layer in a third emission area among the plurality of emission areas, a first dam at an outer portion of the bank, a second dam at an outer portion of the first dam, a dummy light-emitting layer between the first dam and the second dam, and a sealant overlapping the dummy light-emitting layer, the sealant being between the first dam and the second dam.

Abstract: A method is presented for incorporating a resistive random access memory (RRAM) stack within a resistive memory crossbar array. The method includes forming a conductive line within an interlayer dielectric (ILD), constructing a barrier layer over a portion of the conductive line, forming a bottom meshed electrode, depositing a dielectric layer over the bottom meshed electrode, and forming a top meshed electrode over the dielectric layer, where each of the top and bottom meshed electrodes includes a plurality of isolations films.

Abstract: A light emitting device includes: light emitting cells arranged in column and row directions, each including a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first insulation layer continuously disposed on the light emitting cells and having, in each light emitting cell, a first hole on the first semiconductor layer exposed from the second semiconductor layer and a second hole on the second semiconductor layer; a wiring electrode having light reflectivity, covering the first insulation layer, and electrically connected with the first semiconductor layer at the first hole in each light emitting cell; and a second electrode disposed in each light emitting cell and electrically connected with the second semiconductor layer at the second hole. The first insulation layer is exposed from the first semiconductor layer between the light emitting cells. The lower face of the first semiconductor layer has a roughened surface.

Abstract: A method is presented for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET). The method includes constructing a first set fins from a first material, constructing a second set of fins from a second material, forming a source region between the first set of fins, and forming a drain region between the second set of fins, the source region composed of a different material than the drain region. The method further includes depositing a first high-k metal gate over the first set of fins and depositing a second high-k metal gate over the second set of fins, the second high-k metal gate being different than the first high-k metal gate such that the asymmetric threshold voltage is present along the channel of the VTFET in a region defined at the bottom of the first and second set of fins.

Abstract: A display substrate, a method for manufacturing the same and a display device are provided. The method includes steps of forming a common electrode line, a semiconductor pattern, and a data line on a base substrate, so that the semiconductor pattern is located between the common electrode line and the data line; and irradiating the semiconductor pattern by using light in a predetermined wavelength range from a side of the base substrate distal to the semiconductor pattern, to generate a dangling-bond defect state in a band gap of the semiconductor pattern.

Abstract: A quantum dot structure having a split-gate geometry is provided. The quantum dot is configured for incorporation into a quantum dot array of a quantum processing unit. A gap between a reservoir accumulation gate and a quantum dot accumulation gate provides a tunnel barrier between an electric charge reservoir and a quantum dot well. An electrical potential applied to the gates defines a tunnel barrier height, width and charge tunneling rate between the well and the reservoir without relying on any barrier gate to control the charge tunneling rate.

Abstract: A method of fabricating a rigid island pattern on a stretchable layer having a low Young's modulus and a stretchable electronic device platform using the same are disclosed. The stretchable electronic device platform, which is proposed by the present disclosure and has the rigid island pattern on the stretchable layer having a low Young's modulus, includes a stretchable substrate having a first Young's modulus, a Silbione® layer coated with a stretchable layer having a Young's modulus lower than the first Young's modulus on the stretchable substrate, and a fixed layer which is made of a photoresist such as SU-8 or a UV curable resin and has a Young's modulus higher than the first Young's modulus, and in which the rigid island pattern and the meandering stretchable interconnector pattern are formed on the stretchable layer by a photolithography process.

Abstract: Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. The semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. The second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material.

Abstract: The technical field of liquid crystal display is related to. A pixel unit is provided. The pixel unit includes a storage capacitor that is arranged on an array substrate. The storage capacitor includes a first electrode arranged on a first metal layer and a second electrode arranged on a second metal layer. An insulation layer is arranged between the first electrode and the second electrode. The second electrode and the first electrode overlap with each other to form a first overlapping region, an area of which does not change if a deviation of the second electrode relative to the first electrode is within a preset distance. Storage capacitor difference among different pixel units generated by alignment accuracy difference thereof can be eliminated, and watermark which would be generated otherwise can be eliminated as well. An array substrate is further provided, which includes the storage capacitor of the aforesaid pixel unit. A quality of a product can be improved.

Abstract: A back-illuminated image sensor includes a first pixel, a second pixel, and a channel stop situated between the first pixel and the second pixel to isolate the first pixel from the second pixel. The channel stop includes a LOCOS structure and a region of doped silicon beneath the LOCOS structure. The back-illuminated image sensor also includes a first electrically conductive contact that extends through the LOCOS structure and forms an ohmic contact with the region of doped silicon. The first electrically conductive contact may be grounded, negatively biased, or positively biased, depending on the application.

Abstract: A method of forming a semiconductor structure includes forming a first pattern of alternating spacers of a first material and a second material on a semiconductor substrate, forming a second pattern of the alternating spacers of the first material and the second material by selectively removing at least a portion of at least one of one or more of the spacers of the first material and one or more of the spacers of the second material to form a remaining pattern of spacers of the first material and the second material on the semiconductor substrate, and transferring the second pattern of the spacers of the first material and the second material to the semiconductor substrate to form two or more fins in the semiconductor substrate by etching the semiconductor substrate selective to the first material and the second material.

Abstract: A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. A second die is stacked above the first die. The first die, the second die and the package substrate form a first package. An IC is placed within a close proximity of the first package where the first die communicates with the second die at a first data rate while the first die communicates with the IC at a second data rate. The first data rate is higher than the second data rate. Methods of forming a multi-access memory system are also disclosed.