Abstract: A structure and an operation of a transistor, which is a vertical transistor in which a nanowire-type floating body layer is vertically formed or a horizontal transistor in which a floating body layer is horizontally formed, and implements a spike operation of a neuron by storing and releasing charges inside the transistor, and a neuromorphic system using the same are provided. The vertical transistor includes a floating body layer in a form of a vertical nanowire vertically formed on a substrate, a source and a drain formed above and below the floating body layer, a gate insulating layer formed on the source and surrounding the floating body layer, a gate formed outside the gate insulating layer, and a contact metal being in contact with the source, the drain and the gate to input or output an electrical signal.

Abstract: A semiconductor structure includes a substrate, a first word line structure, a second word line structure, a third word line structure, and a fourth word line structure. The substrate has an active region surrounded by an isolation structure. The first and second word line structures are disposed in the active region and separated from each other. The third and fourth word line structures are disposed in the isolation structure, and each of the third and the fourth word line structures includes a bottom work-function layer, a middle work-function layer on the bottom work-function layer, and a top work function layer on the work-function middle layer. The middle work-function layer has a work-function that is higher than a work-function of the top work-function layer and a work-function of the bottom work-function layer.

Abstract: An electronic module has a first substrate 11, a first electronic element 13 provided on one side of the first substrate 11, a first connection body 60 provided on one side of the first electronic element 13, a second electronic element 23 provided on one side of the first connection body 60, a second substrate 21 provided on one side of the second electronic element 23, and an abutment body 250 that abuts on a face on one side of the second electronic element 23 and is capable of imparting a force toward one side with respect to the second substrate 21.

Abstract: An array substrate, comprises: a plurality of test leads correspondingly connected to a plurality of signal lines respectively through an electrostatic protection circuit; a plurality of driving chip binding pads, which are correspondingly connected to the plurality of test leads respectively through driving signal leads, and are configured to input a driving signal sent from a driving chip to the plurality of signal lines through the plurality of test leads; and the electrostatic protection circuit, which comprises a first connection terminal electrically connected to the plurality of test leads, and a second connection terminal electrically connected to the plurality of signal lines.

Abstract: A transistor is provided and includes a substrate; a first interlayer dielectric layer disposed on the substrate, the first interlayer dielectric layer including an opening there-through; a work function layer at least disposed over a bottom of the opening; a gate electrode layer disposed in the opening and over the work function layer; and a protection layer disposed on the work function layer and between the gate electrode layer and the first interlayer dielectric layer.

Abstract: Disclosed is a display device comprising: a substrate comprising an active region and a non-active region; a light emitting device that emits light in the active area of the substrate; a touch sensor in the active area of the substrate that senses touch of the display device, the touch sensor including a plurality of conductive layers arranged in a stacking sequence; and a plurality of routing lines in the non-active region of the substrate that are connected to the touch sensor, each of the plurality of routing lines including a plurality of routing layers, each of the plurality of routing layers made of a same material as a corresponding one of the plurality of conductive layers included in the touch sensor, and the plurality of routing layers arranged in a same stacking sequence as the stacking sequence of the plurality of conductive layers of the touch sensor.

Abstract: Disclosed are exemplary embodiments of compressible foamed thermal interface materials. Also disclosed are methods of making and using compressible foamed thermal interface materials.

Abstract: Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a system is provided that has a circuit board with a pocket and a conductor layer. A chiplet is positioned in the pocket. The chiplet has plural bottom side interconnects electrically connected to the conductor layer and plural top side interconnects adapted to interconnect with two or more semiconductor chips.

Abstract: An electronic device is mountable on a substrate. The substrate includes a first layer and a second layer located on a lower surface of the first layer. The first layer includes a plurality of first through-cavities. The second layer includes at least one second through-cavity overlapping the plurality of first through-cavities in a plan view. The plurality of first through-cavities are continuous with the at least one second through-cavity.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a first oxide layer in the trench; forming a silicon layer on the first oxide layer; performing an oxidation process to transform the silicon layer into a second oxide layer; and planarizing the second oxide layer and the first oxide layer to form a shallow trench isolation (STI).

Abstract: A semiconductor device includes a coaxial contact that has conductive layers extending from local interconnects and being coupled to metal layers. The local interconnects are stacked over a substrate and extend laterally along a top surface of the substrate. The metal layers are stacked over the local interconnects and extend laterally along the top surface of the substrate. The conductive layers are close-shaped and concentrically arranged, where each of the local interconnects is coupled to a corresponding conductive layer, and each of the conductive layers is coupled to a corresponding metal layer. The semiconductor device also includes insulating layers that are close-shaped, concentrically arranged, and positioned alternately with respect to the conductive layers so that the conductive layers are spaced apart from one another by the insulating layers.

Abstract: Some embodiments relate an integrated circuit (IC). The IC includes a first substrate including an array of photodetectors, wherein a bond pad opening extends through the first substrate and is defined by an inner sidewall of the first substrate. An interconnect structure is disposed over the first substrate and includes a plurality of metal layers stacked over one another and disposed within a dielectric structure. The bond pad opening further extends through at least a portion of the interconnect structure and is further defined by an inner sidewall of the interconnect structure. A bond pad structure directly contacts a metal layer of the plurality of metal layers in the interconnect structure and is located at an uppermost extent of the bond pad opening.

Abstract: A neuromorphic computing device includes synapse weights. The synapse weights have different weight values resulted from different transistor arrangements of the synapse weights.

Abstract: A head mounted display device comprises a display panel comprising first to third subpixels defined at a substrate, a reflection plate provided in the first, second and third subpixels, first electrodes vertically spaced apart from a lower surface of the reflection plate by a first distance, a second distance and a third distance at the first, second and third subpixels, respectively, a white organic stack on the first electrodes at the first, second and third subpixels, a second electrode on the white organic stack, and a first color filter on the second electrode at the third subpixel to transmit light having a long wavelength.

Abstract: The present invention provides an array substrate and a display panel. The array substrate includes a fan-out region, an array test region having multiple array test pads and multiple test switches, and a cell test region having multiple cell test pads and a dummy pad. A control end of each test switch is connected to the dummy pad, and the array test pads are connected to the first signal lines through the test switches. According to a high-level signal or a low-level signal received by the dummy pad, the test switch is turned on or off to conduct an array test or a cell test.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Abstract: Techniques are disclosed for forming a heterojunction bipolar transistor (HBT) that includes a laterally grown epitaxial (LEO) base layer that is disposed between corresponding emitter and collector layers. Laterally growing the base layer of the HBT improves electrical and physical contact between electrical contacts to associated portions of the HBT device (e.g., a collector). By improving the quality of electrical and physical contact between a layer of an HBT device and corresponding electrical contacts, integrated circuits using HBTs are better able to operate at gigahertz frequency switching rates used for modern wireless communications.

Abstract: In described examples, a cavity is formed between a substrate and a cap. One or more access holes are formed through the cap for removing portions of a sacrificial layer from within the cavity. A cover is supported by the cap, where the cover is for occulting the one or more access holes along a perspective. An encapsulant seals the cavity, where the encapsulant encapsulates the cover and the one or more access holes.