Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

Abstract: The present disclosure relates to a semiconductor device and method of manufacturing the same. The semiconductor device includes a substrate and a through silicon via structure. The through silicon via is disposed in the substrate and includes an insulation layer and a plurality of conductive lines. The conductive lines are separated from each other by the insulation layer and extend from a top surface of the insulation layer to a bottom surface opposite to the top surface.

Abstract: An alternating stack of insulating layers and word-line-level spacer material layers is formed over a substrate. Memory opening fill structures including a respective memory film, a respective word-line-level semiconductor channel portion, a respective word-line-level dielectric core laterally, and a respective sacrificial dielectric material portion are formed through the alternating stack. Drain-select-level material layers are formed over the alternating stack and the memory opening fill structures. Drain-select-level openings are formed through the drain-select-level material layers and over the memory opening fill structures. The sacrificial dielectric material portions are removed selective to the word-line-level semiconductor channel portions underneath the drain-select-level openings. Drain-select-level semiconductor channel portions are formed directly on a respective one of the word-line-level semiconductor channel portions.

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

Abstract: A novel semiconductor device formed with single-polarity circuits using OS transistors is provided. Thus, connection between different layers in a memory circuit is unnecessary. This can reduce the number of connection portions and improve the flexibility of circuit layout and the reliability of the OS transistors. In particular, many memory cells are provided; thus, the memory cells are formed with single-polarity circuits, whereby the number of connection portions can be significantly reduced. Further, by providing a driver circuit in the same layer as the cell array, many wirings for connecting the driver circuit and the cell array can be prevented from being provided between layers, and the number of connection portions can be further reduced. An interposer provided with a plurality of integrated circuits can function as one electronic component.

Abstract: Methods and apparatus for enhancing simulated annealing with quantum fluctuations. In one aspect, a method includes obtaining an input state; performing simulated annealing on the input state with a temperature reduction schedule until a decrease in energy is below a first minimum value; terminating the simulated annealing in response to determining that the decrease in energy is below the first minimum level; outputting a first evolved state and first temperature value; reducing the temperature to a minimum temperature value; performing quantum annealing on the first evolved state with a transversal field increase schedule until a completion of a second event occurs; terminating the quantum annealing in response to determining that a completion of the second event has occurred; outputting a second evolved state as a subsequent input state for the simulated annealing, and determining that the completion of the first event has occurred.

Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, an insulating layer provided on the nitride semiconductor layer, a first region provided in the nitride semiconductor layer, and a second region which is provided between the first region in the nitride semiconductor layer and the insulating layer, has a higher electric resistivity than the first region, and includes carbon (C).

Abstract: A method is presented for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET). The method includes constructing a first set fins from a first material, constructing a second set of fins from a second material, forming a source region between the first set of fins, and forming a drain region between the second set of fins, the source region composed of a different material than the drain region. The method further includes depositing a first high-k metal gate over the first set of fins and depositing a second high-k metal gate over the second set of fins, the second high-k metal gate being different than the first high-k metal gate such that the asymmetric threshold voltage is present along the channel of the VTFET in a region defined at the bottom of the first and second set of fins.

Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

Abstract: A method for directly bonding a first and a second substrate. The method comprises removing surface oxide layers from bonding faces of the first and of the second substrate, and hydrogen passivation of the bonding faces, then, in a vacuum, electron impact hydrogen desorption on the bonding faces followed by placement of the bonding faces in intimate contact with one another.

Abstract: An embodiment of the invention may include a method, computer program product and computer system for neural activity interpretation. The method, computer program product and computer system may include a computing device that presents a first user with a stimulus and monitors and maps the neural activity of the first user. The computing device may receive the first user's verbal reaction to the stimulus and map the linguistic data of the first user's verbal reaction to form a high dimensional vector based on the relationships of the mapped neural activity and the mapped verbal reaction of the first user. The computing device may associate the high dimensional vector with the stimulus presented resulting in a thoughts model. The computing device may receive a second user's neural activity and compare that second user's neural activity to the thoughts model to identify the neural activity in the second user.

Abstract: Multiple Josephson toroidal vertex quantum superconductive/memristive and superconductive/memcapacitive devices were invented with various superlattice structures, which work at room temperature without an applied external magnetic flux. The first type of the superlattices of the devices comprises of multiple-layers of organometallic polymers on gold chips by self-assembling that mimics the function of Matrix Metalloproteinase-2 (MMP-2). Another type of quantum superconductor/memristor comprises of multiple-organic polymers cross-linked with MMP-2 protein forming Josephson toroidal vertex on the gold surface. Models of the quantum superconductive/memristive and superconductive/memcapacitive devices were fabricated in nano superlattice structures and the devices module configurations were described. Three different methods were used to evaluate the devices' applications in sub fg/mL collagen-1 sensing, energy storage, and the super-position characteristics as a potential quantum bit device.

Abstract: A method is presented for incorporating a resistive random access memory (RRAM) stack within a resistive memory crossbar array. The method includes forming a conductive line within an interlayer dielectric (ILD), constructing a barrier layer over a portion of the conductive line, forming a bottom meshed electrode, depositing a dielectric layer over the bottom meshed electrode, and forming a top meshed electrode over the dielectric layer, where each of the top and bottom meshed electrodes includes a plurality of isolations films.

Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive pillar over a redistribution structure. The method includes bonding a chip to the redistribution structure. The method includes forming a molding layer over the redistribution structure. The molding layer surrounds the conductive pillar and the chip, and the conductive pillar passes through the molding layer. The method includes forming a cap layer over the molding layer and the conductive pillar. The cap layer has a through hole exposing the conductive pillar, and the cap layer includes fibers. The method includes forming a conductive via structure in the through hole. The conductive via structure is connected to the conductive pillar.

Abstract: An embodiment of the invention may include a method, computer program product and computer system for neural activity interpretation. The method, computer program product and computer system may include a computing device that presents a first user with a stimulus and monitors and maps the neural activity of the first user. The computing device may receive the first user's verbal reaction to the stimulus and map the linguistic data of the first user's verbal reaction to form a high dimensional vector based on the relationships of the mapped neural activity and the mapped verbal reaction of the first user. The computing device may associate the high dimensional vector with the stimulus presented resulting in a thoughts model. The computing device may receive a second user's neural activity and compare that second user's neural activity to the thoughts model to identify the neural activity in the second user.

Abstract: A semiconductor package includes: a semiconductor chip having an active surface, having connection pads disposed thereon, and an inactive surface, opposing the active surface; an encapsulant covering the inactive surface of the semiconductor chip; a thermally conductive via penetrating through at least a portion of the encapsulant on the inactive surface of the semiconductor chip and physically spaced apart from the inactive surface of the semiconductor chip; and a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads.

Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate, a first doped region, and a second doped region at least partially in the substrate, and a contact plug directly over the gate, a first metal interconnect composed of copper over the transistor region, and a magnetic tunneling junction (MTJ) directly over the contact plug and under the first metal interconnect.

Abstract: A chip package may include a first polymer layer and a first semiconductor chip in the first polymer layer. The first semiconductor chip may include a first semiconductor device and a first semiconductor substrate supporting the first semiconductor device. The first semiconductor chip may also have a first contact pad coupled to the first semiconductor device. The first semiconductor chip may further include a first conductive interconnect on the first contact pad. The chip package may also include a second polymer layer on the first polymer layer and across an edge of the first semiconductor chip. The chip package may further include a first conductive layer in the second polymer layer and directly on a surface of the first conductive interconnect, and across the edge of the first semiconductor chip.

Abstract: A device, system and method for producing enhanced external quantum efficiency (EQE) LED emission are disclosed. The device, system and method include a patterned layer configured to transform surface modes into directional radiation, a semiconductor layer formed as a III/V direct bandgap semiconductor to produce radiation, and a metal back reflector layer configured to reflect incident radiation. The patterned layer may be one-dimensional, two-dimensional or three-dimensional. The patterned layer may be submerged within the semiconductor layer or within the dielectric layer. The semiconductor layer is p-type gallium nitride (GaN). The patterned layer may be a hyperbolic metamaterials (HMM) layer and may include Photonic Hypercrystal (PhHc), or may be a low or high refractive index material or may be a metal.

Abstract: A semiconductor package device includes a circuit layer having a top surface, a first electronic component disposed on the top surface of the circuit layer, and a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface. The first electronic component has an active surface and a back surface facing the top surface of the circuit layer. A distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer.