Abstract: A power beaming system includes a power beam reception unit and a power beam transmission unit. The power beam reception unit includes a power conversion array, such as a photovoltaic array, arranged to capture at least a portion of a power beam, and a power supply circuit arranged to convert flux from the captured portion of the power beam to electric power. The power beam transmission unit includes a power beam transmitter circuit to transmit a low-flux search beam during a first time window, and further arranged to transmit a high-flux power beam during a second time window. The power beam transmission unit also includes a location detection circuit arranged to identify a location of the reception unit based on the power beam transmitter circuit transmitting the low-flux search beam during the first time window.

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Abstract: Apparatuses and methods for quadrature signal generation are provided. An example includes a quadrature signal generator. The quadrature signal generator is configured to generate, based on a received differential signal, a plurality of quadrature clock signals at a same frequency as that of the received differential signal. The quadrature signal generator is also configured to provide the plurality of quadrature clock signals to a memory system.

Abstract: Embodiments herein may present an integrated circuit including a switch, where the switch together with other switches forms a network of switches to perform a sequence of operations according to a structure of a collective tree. The switch includes a first number of input ports, a second number of output ports, a configurable crossbar to selectively couple the first number of input ports to the second number of output ports, and a computation engine coupled to the first number of input ports, the second number of output ports, and the crossbar. The computation engine of the switch performs an operation corresponding to an operation represented by a node of the collective tree. The switch further includes one or more registers to selectively configure the first number of input ports and the configurable crossbar. Other embodiments may be described and/or claimed.

Abstract: In certain aspects, an apparatus includes a first plurality of power switch devices. Each of the first plurality of power switch devices includes a delay line having a programmable time delay, and a power switch coupled between a supply rail and a circuit block, wherein the power switch has a control input coupled to the delay line. The apparatus also includes a switch manager configured to program the time delays of the delay lines in the first plurality of power switch devices based on a number of active circuit blocks in a system.

Abstract: Provided are embodiments including methods, systems, and computer-program products for mitigating power supply noise using one or more current supplies. In some embodiments, power is provided to an integrated circuit, wherein a first circuit is coupled to the integrated circuit over a first path. A variation of the current level of the integrated circuit may be determined. Additional power from a second circuit is provided to the integrated circuit may be provided based at least in part on the determined variation, wherein the second circuit is coupled to the integrated circuit over a second path.

Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

Abstract: Disclosed is a high-speed track-and-hold device including a buffer stage circuit including a PMOS source follower and a post linear circuit, and a sampling stage circuit that is responsible for supplying a source voltage (VSS) to the buffer stage circuit and that is arranged so that a switch connected to a gate is connected to the source voltage (VSS) and the NMOS transistor of a sampling stage is turned off in hold operation.

Abstract: A level shifter includes (a) an input unit including (i) a first input transistor configured to receive a first voltage and connected to a first connection node, and (ii) a second input transistor configured to receive the first voltage and connected to a second connection node, (b) an output unit including (i) a first output transistor connected to a first output terminal and configured to receive a second voltage, and (ii) a second output transistor connected to a second output terminal and configured to receive the second voltage, (c) a first bias unit configured to control voltage drop between the output terminals and the connection nodes based on a first bias signal, and (d) a second bias unit configured to control a first voltage drop between the first output transistor and the second output terminal and a second voltage drop between the second output transistor and the first output terminal based on a second bias signal.

Abstract: A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.

Abstract: In a monitor circuit, a data signal is propagated from an FF to another FF via a data delay circuit. The data delay circuit selects any one from among data paths that delay the data signal in accordance with a selection signal. A clock signal that is input to the FF is input to the other FF via a clock delay circuit. The clock delay circuit selects any one from among clock paths that delay the clock signal in accordance with another selection signal.

Abstract: A divider circuit and method for generating one or more digital signals is presented. The circuit has a first output section for generating a first digital signal. There is a first output section with an output node to output the first digital signal, and a plurality of switches with one or more control switches. The plurality of switches selectively couple the output node to a first voltage and/or to selectively couple the output node to a second voltage, thereby generating the first digital signal. The or each control switch is prevents at least one of (i) the output node being coupled to the first and second voltages simultaneously and (ii) the output node being decoupled from both the first and second voltages simultaneously.

Abstract: A band-pass filter is described comprising a first first-order filter stage comprising a first resistor characterized by a first impedance and connected to a first node, referred to as a filter input node, and, through a second node to a first reactive component connected to a third node, the first impedance being such that a first current therethrough is dependent on the difference between the voltages at the first and second nodes; and a second first-order filter stage comprising a second resistor characterized by a second impedance and connected to the second node, and, through a fourth node, to a second reactive component connected to a fifth node. The second impedance is such that a second current therethrough is dependent on the negative of the sum of the voltages at the second and fourth nodes. The band-pass filter further comprises summing means for summing the voltages at the second and fourth nodes to output a voltage at a sixth node.

Abstract: A first current proportional to absolute temperature flows in a first current line through a first p-n junction and a second p-n junction arranged in series. A cascaded arrangement of p-n junctions is coupled to the second p-n junction and includes a further p-n junction with a current flowing therethrough that has a third order proportionality on absolute temperature. A differential circuit has a first input coupled to the further p-n junction and a second input coupled to a current mirror from the first p-n junction, with the differential circuit configured to generate a bandgap voltage with a low temperature drift from a sum of first voltage (that is PTAT) derived from the first current and a second voltage (that is PTAT3) derived from the third current.

Abstract: An internal voltage generation circuit includes a counting operation control signal generation circuit and a drive control signal generation circuit. The counting operation control signal generation circuit compares a test internal voltage with a test reference voltage to generate a counting operation control signal in a test mode. The drive control signal generation circuit generates a drive adjustment signal whose logic level combination is adjusted according to the counting operation control signal in the test mode. In addition, the drive control signal generation circuit compares the test internal voltage with the test reference voltage in the test mode to generate a drive control signal for driving the test internal voltage.

Abstract: A power switch configured to apply power to a device is described. The power comprises a switching module having a switch for selectively applying power to a device based upon control signals; and a control module removably coupled to the switching module and in communication with the switching module when the control module is attached to the switching module; wherein the control module comprises a wireless communication circuit and provides the control signals to the switching module to enable a switching operation of the power switch. A method of implementing a power switch configured to apply power to a device is also described.

Abstract: A circuit includes a first TSCP (tri-state charge pump) configured to receive a first phase and a third phase of a six-phase signal; a second TSCP configured to receive a second phase and a fourth phase of the six-phase signal; a third TSCP configured to receive a third phase and a fifth phase of the six-phase signal; a fourth TSCP configured to receive a fourth phase and a sixth phase, a fifth TSCP configured to receive the fifth phase and the first phase, and a sixth TSCP configured to receive the sixth phase and the second phase of the six-phase signal. The first, third, and fifth TSCPs output currents to a first output node and the second, fourth, and sixth TSCPs output currents to a second output node. A load is placed across the first output node and the second output node.

Abstract: The invention comprises a fault-tolerant clock synchronization method with high precision, hardware implementations thereof and the corresponding digital circuits, designed to contain metastability.

Abstract: A system may include first and second node, switch, driver, capacitor, and second driver. The first node may be at first voltage. The second node may be at second voltage. The switch may be coupled to the second node and output of the second driver and configured to receive input at third voltage and voltage at fourth voltage and to provide the input to the second node when the fourth voltage is greater than the third voltage. The driver may be coupled to the first and second nodes and configured to receive driver input and to generate intermediate voltage based on the driver input. The capacitor may be coupled to the driver to shift the intermediate voltage. The second driver may be coupled to the second node and the driver and configured to receive second driver input and the shifted intermediate voltage to generate the voltage at the fourth voltage.

Abstract: Power transfer systems including a direct current source and a plurality of outputs operable in several modes. A ground mode may couple an output to circuit ground and a current mode may couple the output to the direct current source. The power transfer system may also include a controller configured to iteratively select a pair of outputs from the plurality of outputs. Once a pair is selected, the controller may set a first output of the pair of outputs to the current mode and the second to ground mode for a determined duration. After the duration has passed, the controller may set the first output to the ground mode and the second output to the current mode for the same duration. Thereafter the controller may select another pair of outputs.