Abstract: Apparatus and associated methods relate to a consolidated power-on-reset system (PORS) at a system-on-chip (SoC) level. In an illustrative example, an integrated circuit may include a first power domain and a second power region. A level shifter circuit may be coupled to translate data from the first power domain to the second power domain. A PORS including a voltage detection circuit, a glitch filter circuit, and logic gates may be configured to generate isolation signals between the first power domain and the second power domain. The level shifter circuit may be enabled in response to the generated isolation signals. By using the isolation signals, multiple power domains on IC may be managed comprehensively during power-up to avoid unstable operation.

Abstract: A wireless communication device associated with a mobile operator network transmits an authentication request for network access via a wireless access point (AP) using a network transceiver or a transceiver other than the cellular network transceiver. Device authentication can occur directly with the mobile operator network or via a proxy server. Communications with the authentication server my use VLAN/VRF or NFV depending on the availability of the network communications technology. Upon authentication, the requesting device may access a wide area network in a data off-load operational mode and the data flow to and from the device via the AP is monitored and reported to mobile operator network associated with the requesting device. The wireless communication device can communicate with any of a plurality of APs distributed in a venue during the data off-load operational mode.

Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.

Abstract: A gate driver circuit includes an input terminal for receiving an input switching signal for driving a switching circuit that has a high-side transistor and a low-side transistor vertically stacked. The gate driver circuit also includes a dead-time control circuit, that includes two dead-time measurement circuits. The first dead-time measurement circuit produces a first pulse signal having a first pulse width representing a first dead-time between when a gate voltage of the low-side transistor falls below a first threshold voltage and when a gate voltage of the high-side transistor rises above a second threshold voltage. The second dead-time measurement circuit produces a second pulse signal having a second pulse width representing a second dead-time between when the gate voltage of the high-side transistor falls below the second threshold voltage and when the gate voltage of the low-side transistor rises above the second threshold voltage.

Abstract: Systems and methods for increasing the RF power switched into a resonant load by achieving voltage multiplication by means of coupled inductors are provided herein. In one approach, the RF electromagnetic wave achieved by voltage multiplication is used to drive a diode opening switch in order to create a fast rising, unipolar electrical pulse.

Abstract: A transistor-based radio frequency (RF) switch that provides symmetric RF impedance is disclosed. The transistor-based RF switch includes an N number of main field-effect transistors (FETs) stacked in series between a first end node and a second end node. A first end-network is coupled between the first end node and a proximal gate node. The first end-network provides a first variable impedance that equalizes a drain-to-source voltage of the first main FET to within a predetermined percentage of a drain-to-source voltage of a second main FET of the N number of main FETs. A second end-network is coupled between the second end node and the distal gate node, wherein the second end-network provides a second variable impedance to equalize the drain-to-source voltage of an Nth main FET to within the predetermined percentage of the drain-to-source voltage of an N?1 main FET of the N number of main FETs.

Abstract: A bridge output circuit includes: a voltage-controlled first transistor provided between a first power supply terminal and an output terminal; a voltage-controlled second transistor provided between the output terminal and a second power supply terminal having a potential lower than the potential of the first power supply terminal; a first OFF detection circuit detecting whether the first transistor is in an OFF state based on a gate voltage of the first transistor; a second OFF detection circuit detecting whether the second transistor is in an OFF state based on a gate voltage of the second transistor; and an output control circuit performing a first source transition operation of turning off the second transistor and then turning on the first transistor, and then performing a second source transition operation of turning off the first transistor and then turning on the second transistor.

Abstract: A power transmitting apparatus that transmits power to a power receiving apparatus executes intermittent wireless transmission of power. The power transmitting apparatus operates according to one of a first power transmitting method including detecting a signal load-modulated by the power receiving apparatus using an ID in response to the transmitted power during the intermittent transmission and a second power transmitting method including transmitting the power having modulated the power according to an ID determined in advance so that the power receiving apparatus detects the ID determined in advance.

Abstract: A rectifier IC includes, in a single package, a transistor chip in which a transistor is integrated, a controller chip that detects a drain voltage (VD) and a source voltage (VS) of the transistor so as to perform ON/OFF control of the transistor, and functions as secondary side rectifier means of an insulation type switching power supply. The controller chip turns on the transistor when VD is lower than VS and turns off the transistor when VD is higher than VS. The insulation type switching power supply includes a transformer supplied with an input voltage, a control unit that controls primary side current of the transformer according to a feedback signal, a rectifying and a smoothing unit that rectifies and smooths a secondary side voltage of the transformer so as to generate an output voltage, and an output feedback unit that generates the feedback signal according to the output voltage.

Abstract: Systems and methods for quickly charging a load capacitance to a voltage level that is a multiple of the DC input voltage are provided herein. In one approach, the load capacitance is charged by a voltage multiplication circuit, and the load capacitance is subsequently discharged into a resonant circuit that drives a diode opening switch in order to create a fast rising, unipolar electrical pulse.

Abstract: A gate driver circuit includes a gate driver and a sensing circuit. The gate driver is configured to generate an on-current during a plurality of turn-on switching events to drive a transistor, where a voltage across the transistor changes from a first value to a second value with a slope during the plurality of turn-on switching events, where the slope is of either an active type dependent on an amplitude of the on-current or a passive type. The sensing circuit determines whether the slope during a first turn-on switching event is the active type or the passive type, and regulates the amplitude of the on-current during a second turn-on switching event that is subsequent to the first turn-on switching event if the slope is the active type and to maintain the amplitude of the on-current as unchanged during the second turn-on switching event if the slope is the passive type.

Abstract: A programmable delay line includes a pulse generator configured to generate a pulse in response to a transition of an input signal; an oscillator configured to generate a clock in response to the pulse; a counter configured to change a current count from a first value towards a second value in response to periods of the clock; and a gating device configured to output the transition of the input signal to generate an output signal in response to the current count reaching the second value. The delay of the input signal is a function of the difference between the first value and the second value. The delay line may be used in different applications, such as a dynamic variation monitor (DVM) configured to detect supply voltage droop. The DVM may be in an adaptive clock distribution (ACD) to reduce the clock frequency for a datapath in response to a droop.

Abstract: A light switch cover for converting a standard toggle switch into a remote-controlled toggle switch.

Abstract: An electronic device includes a first semiconductor die with a first FET having a drain connected to a switching node, a source connected to a reference node, and a gate connected to a first switch control node. The first die also includes a diode-connected bipolar transistor that forms a temperature diode next to the first FET. The temperature diode includes a cathode connected to the reference node, and an anode connected to a bias node. The electronic device also includes a second semiconductor die with a second FET, and a package structure that encloses the first and second semiconductor dies.

Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

Abstract: A power switch circuit includes a first switch circuit, a second switch unit and a capacitor. The capacitor has a first terminal coupled to a node between the first and second switch units. In addition, the capacitor has a second terminal coupled to the first and second switch units, a charge pump and a charging circuit. When the power switch circuit is coupled to a load, the charging circuit pre-charges the capacitor. Once the load is enabled, the first and second switch units are turned on by only a small voltage increase at the second terminal of the capacitor by the charge pump to allow power to be supplied to a load through the first and second switch units from a power supply.

Abstract: A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.

Abstract: Systems, methods, and apparatus for a circuit for synchronization of a reference signal and an output signal of a phased-lock loop (PLL) are disclosed. The method comprises continuously generating, by a clock detect circuit connected to the PLL, a clock detect signal indicating whether the reference signal of the PLL is present or lost. The method further comprises continuously sampling and storing, by a loop sampler circuit connected to the PLL, a voltage from a loop filter of the PLL, when the reference signal is present. In addition, the method comprises configuring a charge pump of the PLL into a high impedance state, thereby disabling the charge pump, when the clock detect signal indicates that the reference signal is lost. Further, the method comprises supplying the voltage to the PLL to maintain a frequency of the output signal of the PLL, when the reference signal is lost.

Abstract: A random number generator capable of generating a natural random number using a spin-orbit torque (SOT) is provided. The random number generator includes a ferromagnetic metal layer and a spin-orbit torque wiring extending in a first direction crossing a lamination direction of the ferromagnetic metal layer and being joined to the ferromagnetic metal layer, wherein the direction of spins injected from the spin-orbit torque wiring into the ferromagnetic metal layer and an easy magnetization direction of the ferromagnetic metal layer intersect each other.

Abstract: A bi-directional level translator with fast rise and fall times and low current leakage is suitable for use with devices connected using a SPMI bus. The level translator passes signals between first and second voltage domains that operate at different voltage levels. The level translator has a first terminal that receives a first signal A from the first voltage domain and outputs a second signal B to the second voltage domain. A second terminal receives the second signal B and outputs the first signal A. A first switch is located between the first voltage source and the first terminal and a second switch is located between the second voltage source and the second terminal. The first and second switches are operable to reduce current leakage of the level translator.