Abstract: A method and apparatus that allows for controlling operating time of a portable computer system and a peripheral device. A portable computing system that includes a rechargeable power supply and that includes a connection mechanism for coupling to a peripheral device is used to control operating time of the portable computer system and the peripheral device. In one embodiment, a user can choose between maximizing the operating time of the portable computer, maximizing the operating time of the peripheral device, or maximizing the life of the entire system (maximizing the operating time of the portable computer system and the peripheral device). When operating time of the portable computer system is to be maximized, power is sent from the peripheral device to the portable computer system to extend the operating time of the portable computer system.

Abstract: A method for “booting up” a multiple function device that involves first detecting the activation of the multiple function device. A 1st boot algorithm, retrieved from read-only memory, is executed to identify the location of a 2nd boot algorithm. The 2nd boot algorithm, retrieved from a specified location based on the booting inputs, is verified for executability. When the 2nd boot algorithm is executable, it is executed to retrieve the functional algorithms that configure the multiple function device in the desired configuration. When the 2nd boot algorithm is not executable, and the multiple function device is operably coupled to a host, the correct functional algorithm or a default functional algorithm is downloaded and executed to configure the multiple function device. When an executable functional algorithm cannot be retrieved from memory or the host, the multiple function device powers down after a predetermined amount of time.

Abstract: A method and apparatus that allows for controlling operating time of a portable computer system and a peripheral device. A portable computing system that includes a rechargeable power supply and that includes a connection mechanism for coupling to a peripheral device is used to control operating time of the portable computer system and the peripheral device. In one embodiment, a user can choose between maximizing the operating time of the portable computer, maximizing the operating time of the peripheral device, or maximizing the life of the entire system (maximizing the operating time of the portable computer system and the peripheral device). When operating time of the portable computer system is to be maximized, power is sent from the peripheral device to the portable computer system to extend the operating time of the portable computer system.

Abstract: A system and method of booting an embedded system having a processor, nonvolatile memory and a remote media interface connected to the processor. Boot code is executed within the nonvolatile memory. The processor determines if a storage device is connected to the remote media interface and, if a storage device is connected to the remote media interface, program code loaded from the storage device to the processor is executed.

Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

Abstract: A computer apparatus provides control for automatically switching the apparatus between various operating modes requiring varying levels of power consumption. An embedded controller determines whether or not the computer apparatus is in motion (vibration, acceleration, rotation, etc.) on the basis of acceleration information obtained through an accelerometer provided in the computer apparatus. If the computer apparatus is in motion, the embedded controller provides control so as to prevent switching between system operating modes in order to protect certain components of the apparatus from damage which might be caused by switching operating modes while in motion.

Abstract: A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port.

Abstract: A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration.

Abstract: A memory device has a plurality of memory blocks utilized to store data. One of the blocks is used as a hidden memory block to store an operating system program, instead of data. The hidden memory block is designated as a bad block so that data will not be written into the hidden memory block, but a tag associated with the hidden memory block identifies that the hidden memory block contains the operating system program.

Abstract: A power management controller for instantaneous frequency-based microprocessor power management including first and second PLLs, select logic, and source control logic. The first PLL generates a first core source clock signal at a first frequency based on a bus clock signal. The second PLL generates a second core source clock signal at a programmable frequency based on a frequency control signal and the bus clock signal. The select logic selects between the first and second core source clock signals to provide a core clock signal for the microprocessor based on a select signal. The source control logic detects power conditions via at least one power sense signal, provides the frequency control signal according to the power conditions, and provides the select signal. The power management controller enables transition from one power state to another in a single clock cycle, which is significantly faster than conventional power management techniques.

Abstract: A circuit capable of updating the power supply specification of microprocessor and a method thereof are proposed. The circuit is disposed on a computer motherboard, and makes use of downloaded program data of the power supply specification of a new microprocessor a microprocessor is updated. The circuit uses a programmable memory IC to execute the program data of the power supply specification for automatically updating and modifying the required power supply specification of the microprocessor. Through a PWM control unit, a drive unit and a power switch, the required power supply specification of a new microprocessor can be provided for the microprocessor to perform boot actions.

Abstract: Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.

Abstract: A frequency-voltage mechanism for power management including first and second PLLs, select logic, control logic, and voltage control logic. The first PLL generates a first source clock signal at a first frequency based on a bus clock signal. The second PLL generates a second source clock signal at a second frequency based on a first frequency control signal and the bus clock signal. The select logic selects between the first and second source clock signals to provide a core clock signal based on a select signal. The clock control logic detects power conditions via at least one power sense signal, provides the first frequency control signal according to power conditions, and provides the select signal. The voltage control logic adjusts the operating voltage commensurate with frequency of the core clock signal. Power consumption is dynamically adjusted without undue delay while providing significant power efficiency benefits.

Abstract: An optical network terminal includes a sleep logic circuit that assumes responsibility for monitoring off-hook transitions after the AC main power supply has failed for a predetermined period of time. The sleep logic circuit is very low power and, as a result, allows the optical network terminal to remain active and provide lifeline support for a much greater period of time.

Abstract: A circuit for protecting a motherboard if a component is not connected properly to its power source, a startup circuit (50) connected to a switch, and a monitoring circuit (70) monitoring the status of the component. The startup circuit provides a control signal to a power supply (10) via the switch for controlling the power supply providing power to the motherboard. The monitoring circuit outputs a monitoring signal to the switch to control the switch to be on or off, so as to control the transfer of the control signal.

Abstract: An apparatus and method are provided that enable a computing device to make graceful power state transitions that do no impose unnecessary power surge compensations requirements on associated power sources. The apparatus has power control logic that is configured to determine if the computing device is to enter a low power state. The power control logic includes a plurality of stop signals. Each of the plurality of stop signals sequentially indicates that a corresponding clock signal be stopped, where the corresponding clock signal is operatively coupled to a corresponding sector logic element within the computing device.

Abstract: An information handling system (IHS) is provided which includes a wireless section that detects the presence of an available wireless network on which the IHS can communicate. When an initialize scan switch is actuated, the wireless section is powered up to perform a scan while other sections of the IHS remain unpowered. In this manner, an available wireless network can be detected without fully powering up the IHS to check for wireless network connections.

Abstract: A power controller which is installed on each of a plurality of blades in a blade style server computer. Each power controller determines whether the blade it is on can go to a higher power mode without a command from a centralized controller.

Abstract: Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.

Abstract: A clamping apparatus, for use with an actuator, has a housing with a guide track mounted on or formed in the housing. A roller or cam operably engages with the guide track such that the cam can be moved and positioned along the guide track by way of the actuator. At least one pivoting arm is pivotally mounted on the housing adjacent to and spaced from the guide track. Each pivoting arm has an elongate slot adjacent to the shoulder. The elongate slot has two arcuate surfaces positioned parallel to each other and has two end surfaces joining the arcuate surfaces to define a closed loop surface. The cam is positioned within the elongate slot of each pivoting arm to pivot each pivoting arm between a clamped position and a released position as the cam is moved along the guide track and driven against the arcuate surfaces of each pivoting arm.