Abstract: The present invention facilitates the operational management and usability of a portable computing device by providing an apparatus, method and program product to allow a user to select the operational and power state of a device operably connected with a computer and the power state of the computer prior to removing the computer from an apparatus such as a docking station.

Abstract: A microcontroller includes a clock circuit with a register storing clock frequency information corresponding to a low speed or normal mode respectively operated by a low frequency or normal clock, which outputs a first signal according to a value set in the register when the low speed mode is designated during operation in the normal mode, a DRAM holding data, in the low speed mode, by operation in a self-refresh mode, and outputting a confirmation signal indicating switching to that mode, a DRAM circuit switching the DRAM to that mode based on the first signal, a ROM operated in the low speed mode, a remap circuit controlling an address circuit based on the confirmation signal, and outputting a second signal for switching a program execution address from the DRAM to an address of the ROM to control an address space in which a program is executed, the address circuit switching the address space based on the second signal.

Abstract: A distributed power management technique allows controlling power states of devices separated from a power management controller, such as a processor, by an interconnect. The power management controller inserts power state information into an interconnect transaction. An interconnect connected device then extracts the power state information and modifies the power state of the device responsive to the power state information. The power state information can be extracted by a processor that then controls the power state of another device responsive to the power state information.

Abstract: A semiconductor device includes a clock generation unit which generates a clock signal, a first module which asserts a clock-control request signal, and one or more second modules, each of which receives the clock signal and the clock-control request signal, and asserts a clock-control acknowledge signal after stopping an operation thereof upon completion of a currently performed operation in response to the assertion of the clock-control request signal, wherein the clock generation unit selectively changes the clock signal supplied to the one or more second modules in response to assertion of all clock-control acknowledge signals output from the one or more second modules.

Abstract: A data clock for use in data communication between the connected processors and a system clock for use in data processing within the own processor are made independent and asynchronous in clock rate and adjustment between the two clocks is performed by an enable creating unit. According to the data processing enable signal created by the two clocks, a timing of the data processing is controlled and the data is processed at a high speed by the system clock.

Abstract: A managing apparatus has a RAM for storing power saving mode shift time and notifies output apparatuses of the stored power saving mode shift time via a network. Each output apparatus is shifted to a power saving mode when measured time by a built-in timer reaches the notified power saving mode shift time.

Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

Abstract: A system correlates clock signal flight times between a device on a board and a device on a card that is coupled to the board. A board device first trace runs from a clock driver on the board to the card. A board device second trace runs back to the board device.

Abstract: A method and system to allow user applications can access hardware platform-specific configuration information in a generic way. A platform independent framework lies on a layer that interfaces with the operating system layer. Accordingly, when a platform is changed, the operating system layer is notified of the change to facilitate informing the user of the change. This framework also has a plug-in publishing interface that is used to develop platform-specific modules to publish or export hardware configurations to other users. In another embodiment, this framework has a user interface that allows the user to make the necessary changes to the system management and hardware diagnostic tools whenever the platform is changed to ensure that the tools function correctly.

Abstract: A system and method for synchronizing a plurality of processors in a multiprocessor computer platform are disclosed. In one system embodiment, a first processor and a second processor may access a global time value associated with a globally accessible clock counter. Each processor may access its respective local time value and adjust its respective synchronization parametrics, thereby synchronizing the plurality of processors.

Abstract: The clock switch device of the present invention includes: a clock detector for receiving a plurality of clocks and clock selection data designating a clock to be selected, detecting whether or not the clock designated by the clock selection data among the plurality of clocks changes in signal level, and outputting the result as a detection signal; a control register for holding and outputting the clock selection data when the detection signal indicates that the clock designated by the clock selection data changes in signal level; and a selector for receiving the plurality of clocks and selecting a clock corresponding to the output of the control register among the plurality of clocks.

Abstract: Methods and devices for power management of graphics or other computer subsystems are disclosed. In one embodiment, graphics software components are configurable in a manner that allows them to place the graphics subsystem is a “safe” state prior to a suspend event, and back into a “working” state after a resume event, without explicit support from an operating system (OS) power management driver. When operating in the absence of an OS-supplied driver, the graphics driver receives notification of power management events, and sends a message to a support application, which then causes the graphics to enter a quiescent state by taking exclusive ownership of the display and issuing standard device-independent OS graphics calls (for a power-down event) or to relinquish display ownership (for a power-up event). From within this quiescent state the graphics may be safely power managed without adverse effects to the graphics chips and without creating any instabilities in other graphics applications.

Abstract: In the data transmission system 1 for transmitting drive pulse data from a personal computer to an ink jet printer in 8-bit units, the drive pulse data includes 7 bits of pulse width data Hx and 9 bits of pulse interval data Lx. The personal computer reduces pulse interval data, which has an amount of data exceeding 8 bits, in half by shifting the bits one place to the right before transmitting the data to the inkjet printer. The basic time period used for decoding the pulse interval data is set to twice the basic time period used for decoding the pulse width data. The pulse interval data is decoded based on this larger basic time period.

Abstract: An uninterruptible power supply unit can communicate with a computer being in a suspend or sleep state. The uninterruptible power supply unit includes a first unit which transmits a first signal for informing the computer that the power supply from the commercial power is stopped via a first communication interface; and a second unit which transmits a second signal for activating the computer from the suspend or sleep state via second communication interface, the second unit being in an active state when the computer is in the suspend or sleep state.

Abstract: A clock architecture employing redundant clock synthesizers is disclosed. In one embodiment, a computer system includes first and second clock boards. The first clock board may act as a master, generating a system clock signal, while the second clock board acts as a slave. The first clock board may monitor a phase difference between a first crystal clock signal and a feedback clock signal. If the phase difference exceeds a limit, the first crystal clock signal may be inhibited, preventing the first clock board from generating the system clock signal. The second clock board may monitor the system clock board in reference to a feedback clock signal. If the second clock board detects a predetermined number of consecutive missing clock edges, it may enable a second crystal clock signal, which may be used to generate a system clock signal.

Abstract: A system and method are disclosed for controlling the frequency of a common clock which is shared by a plurality of processing elements. The usage of the common clock by each of the plurality of processing elements is measured, and the common clock is controlled to have a frequency determined as a function of the measured common clock usage by the plurality of processing elements.

Abstract: Apparatus forming a computer system or such-like is disclosed that includes a central processing unit (CPU) and a power supply unit. The CPU provides a digital voltage ID (VID) signal output indicative of the power supply voltage that it desires to receive. The power supply unit has a control input for receiving a digital VID signal from the CPU. The power output from the unit is then provided to the CPU at a voltage level in accordance with the received digital VID signal. A VID offset generator is interposed between the CPU and the power supply unit. This receives the digital VID signal from the CPU, and modifies it by applying a positive or negative offset. The modified digital VID signal is then passed to the power supply unit, which supplies a voltage to the CPU as per the modified VID signal, rather than the VID signal originally output by the CPU.

Abstract: Methods and structure for customizable BIOS in a peripheral device adapter. The controller of a peripheral device adapter senses a selection indicative of a desired customized BIOS configuration. BIOS information is updated to reflect the desired customized selection. In one embodiment, customization may be by updating portions of a default BIOS configuration with updated information stored in a selected custom BIOS information element. In another embodiment, each custom BIOS information element may store an entire snapshot of BIOS information customized for a particular application. The selected custom BIOS information may then be copied to a BIOS memory or BIOS memory accesses may be mapped to the selected custom BIOS information element.

Abstract: A processor is disclosed including a register, functional unit(s), and a control unit. The register stores multiple bits, wherein one or more of the bits has a value representing a current electrical power dissipation mode (i.e., power mode) of the processor. The functional unit(s) respond to the power mode signal by altering their electrical power dissipation and issuing an acknowledge signal. The control unit receives a power mode input representing a request to enter a new power mode, and issues the power mode signal in response. The control unit waits for the acknowledge signal(s), and responds to the acknowledge signal(s) by modifying the one or more bits of the register to reflect the new power mode. A method is described for transitioning from a current power mode to a new power mode. A data processing system is disclosed including a peripheral device coupled to the processor.

Abstract: The disclosed embodiments relate to circuits that produce synchronized output signals. An input signal is received and used to produce a delayed input signal. The period of the input signal and the phase difference between the input signal and the delayed input signal are measured. The period of the input signal and the phase difference between the input signal and the delayed input signal are used to construct an output signal.