Abstract: A current generator that provides a first current level to read a configuration parameter of a field device. The current generator also provides a second current level. The first current level is lower in amperage than the second current level. The first current level does not operate the field device. The second current level operates the field device. A current sensor is connected in circuit with the field device. The current sensor reads the configuration parameter associated with the first current level. A method is provided that creates a current that reads a configuration parameter. The current has less than a minimum amplitude to operate necessary to operate a field device. The configuration parameter is read from the field device through employment of the current. The field device is configured through employment of the configuration parameter.

Abstract: An image forming device having a communication unit includes a system control unit which controls the entire image forming apparatus, the system control unit having a CPU that is set in one of a normal mode, a power-saving mode and a sleep mode by controlling a power supply unit. A real-time clock keeps track of hours, minutes and seconds of a current time and outputs a signal indicating the current time. A register stores a return time that indicates a time the CPU is to be switched from one of the power-saving mode and the sleep mode to the normal mode. A comparator compares the current time of the clock with the return time of the register, and outputs, when a match occurs, a control signal to the CPU so that the CPU is switched to the normal mode.

Abstract: A system and method of processor type determination. A reset vector from a processor is identified. Responsive to characteristics of the reset vector, a processor type of the processor is determined.

Abstract: Method and apparatus for controlling a processor in a data processing system is described. In an example, the processor is maintained in a halt condition in response to reset information received from the data processing system (200) (e.g., initialization of an integrated circuit having a processor embedded therein). At least one memory resource in communication with the processor is configured. The processor is then released from the halt condition.

Abstract: In one embodiment, there is provided a method comprising determining a target operating point for an electronic device, the target operating point including a target operating frequency and a target operating voltage; and dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and a current operating voltage to the target operating voltage, wherein during the changing the electronic device is in an active state.

Abstract: A method and related apparatuses provide a virtual runtime interface for modifying basic input/output system (BIOS) settings. A processing system may provide the virtual runtime interface after the processing system has booted an operating system (OS). User input that specifies a modified BIOS setting may be received through the virtual runtime interface. To provide the virtual runtime interface, the system may transition from an OS context to a system management mode (SMM) context, and may determine whether the amount of time spent in the SMM context approaches an SMM time limit. If the amount of time spent in the SMM context approaches the SMM time limit, the system may automatically transition from the SMM context back to the OS context. Other embodiments are described and claimed.

Abstract: Techniques for initializing/reinitializing a device on an expansion card without power cycling the system. More specifically, an instruction set is provided such that a device on an expansion card can be reinitialized without power cycling the system. Further, the instruction set may be implemented to initialize a device on a replacement expansion card. During the system boot, an expansion basic input/output system (BIOS) is copied into the system memory. After the system boot, a copy of the configuration information for the device on the expansion card is saved in a backup file in the system memory. The expansion card can be removed and replaced and the configuration information stored in the backup file in the system memory can be used to configure the replacement device. The copy of the expansion BIOS in the system memory can be reprogrammed such that it can be implemented to initialize the device on the replacement expansion card without power cycling the system.

Abstract: An electronic apparatus includes a clock oscillator which supplies a clock signal, a processor which generates an internal clock on the basis of the clock signal supplied from the clock oscillator, and a control unit which controls a frequency of the internal clock in accordance with a ratio of an executable instruction count per unit time to a clock count per unit time of the internal clock generated by the processor.

Abstract: A distributed power management system for a bus architecture or similar communications network. The system supports multiple low power states and defines entry and exit procedures for maximizing energy savings and communication speed.

Abstract: A method, system, software, and processor for initializing information systems operating in headless and non-headless environments are presented. In one form, an information system includes a server platform operably associated with a platform BIOS and a service processor communicatively coupled to the platform BIOS. The service processor employs a platform boot monitor operable to provide an initialization mode of the server platform and may provide a flash update mode for updating a system BIOS.

Abstract: A data processing network includes a set of servers, at least one switch module to interconnect the servers, and a management module. The management module consults power state information stored in the network following a power transition and restores power to at least some of the servers and switch modules based on the power state information. The power state information prevents the management module from restoring power to servers and switch modules having incompatible communication protocols. In one embodiment, the plurality of servers and the switch modules are hot-swappable modules that are all inserted into a single chassis. In this embodiment, the server modules and at least one switch module share selected resources of the network including system power. The switch modules and servers may employ Ethernet, fiber channel, optical, and serial communication protocols.

Abstract: An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel groups and a code detector for detecting a predetermined code pattern in the serial data stream and generating a code detection output in response thereto. The serialiser/deserialiser can also comprise a transition detector for detecting transitions in the serial data stream and reconstructing a serial data clock therefrom, and for generating a plurality of parallel data clocks from the serial data clock, each parallel data clock having a different phase. The data buffer can be responsive to the code detection output to adjust a parallel data group start position within the serial data stream and to cause a selection of one of the reduced frequency clocks having a phase corresponding to the adjusted parallel data group start position.

Abstract: An embedded processor system including at least one gated power unit including an internal ROM and a power controller that provides one or more gated power signals to selectively provide power to each gated power unit. The power controller provides a gated clock signal to the embedded processor to selectively control power consumption of the processor. The power controller powers down each gated power unit after freezing the processor and then powers up each gated power unit before reactivating the processor. The embedded processor system may include isolation circuitry, such as clamp circuitry or the like, that is operative to minimize current flow into each gated power unit when powered down. The gated power units may include a static function. The ROM of an embedded ROM-based microprocessor system is powered down when the microprocessor is idle to reduce or otherwise eliminate intrinsic leakage.

Abstract: A memory device has a plurality of memory blocks utilized to store data. One of the blocks is used as a hidden memory block to store an operating system program, instead of data. The hidden memory block is designated as a bad block so that data will not be written into the hidden memory block, but a tag associated with the hidden memory block identifies that the hidden memory block contains the operating system program.

Abstract: A present invention provides a PDA with a built-in current limiting device. When powered by a battery, the PDA outputs a current to an external device, wherein the current is within a first current range. When powered by external power through an adapter, the PDA outputs the current to the external device, wherein the current is within a second current range. The first current range is smaller than the second current range. Additionally, a current limiting device built into a PDA is disclosed.

Abstract: A method and apparatus for managing power consumption of a processing unit having an operating system (OS) or software system and access to at least one hardware timer saves power by putting the processing unit into one of at least two low power states when the OS or software system is not expected to do work. A time period for which the software system is not expected to perform work is determined, and a determination is made as to which one of at least two low power states to put the processing unit in, in response to the time period. The hardware timer is configured to facilitate waking up the software system or OS in time for it to perform expected work. The processing unit and software system are transitioned into the chosen low power state. They are transitioned out of the low power state in response to a hardware interrupt.

Abstract: In some embodiments, a method and apparatus for an energy efficient clustered micro-architecture are disclosed. In one embodiment, the method includes the computation of an energy delay2 product for each active instruction scheduler and one or more associated function blocks of a current architecture configuration over a predetermined period. Once the energy delay2 product is computed, the computed product is compared against an energy delay2 product calculated for a prior architecture configuration to determine an effectiveness of the current architecture configuration. Based on the effectiveness of the current architecture configuration, a number of active instruction schedulers and one or more associated functional blocks within the current architecture configuration is adjusted. In one embodiment, the number of active instruction schedulers and one or more associated functional blocks may be increased or decreased to improve power efficiency of the cluster micro-architecture.

Abstract: A boot swap method for multiple processor computer systems utilizes a baseboard management controller (BMC) to manage the abnormal booting problem of multiple processor computer systems. According to the usage state of the central processing unit (CPU) or the basic input/output system (BIOS) stored in read only memory (ROM), a CPU switching procedure or an ROM switching procedure is executed to select an available CPU and BIOS for booting. The method can greatly increase the system stability.

Abstract: A method of operating a computer system on which an application is installed comprises the steps of: verifying whether a predetermined run authorization for the application is present, and, in the absence of said predetermined run authorization, decreasing the speed of execution of the application on the computer system as compared to the speed of execution of the application in the presence of the predetermined run authorization.

Abstract: Disclosed is a system and a method for implementing an extensible firmware interface (EFI). In one embodiment, a system and a method pertain to launching an EFI utility during a boot process of a computer system, and building an EFI layer that resides between an operating system of the computer system and a legacy basic input/output system (BIOS) of the computer system using the EFI utility.