Abstract: The timing system includes a plurality of timing units interconnected to perform a count operation. Software programmable registers interconnect the plurality of timing units, and a control circuit generates a clock signal for the plurality of timing units. The control circuit includes an interface for connection to an external bus to receive and transmit data.

Abstract: An apparatus and method for time synchronization of a plurality of multimedia streams are described. In one embodiment, the method includes the concurrent capture of multimedia data via a plurality of multimedia platforms. During the concurrent capture of the multimedia data, each of the multimedia platforms receives a synchronization signal from a synchronization generation unit. In response, each platform processes a received synchronization signal to generate a common reference clock signal among each of the platforms. Once the common clock signal is generated, each of the platforms synchronizes captured multimedia data to form multimedia stream data according to the common reference clock signal. As such, the plurality of multimedia platforms are able to perform collaborative signal processing tasks of multimedia streams, including, for example, array signal processing algorithms.

Abstract: Method and apparatus are disclosed that allow boot code within the apparatus to be updated using a system controller. The apparatus includes a central processing unit (CPU) and a programmable memory that contains boot code at a predetermined location for use in booting the CPU. The apparatus further includes a bus and a bus master for the bus. The CPU accesses the boot code via the bus and the bus master. The apparatus further includes a system controller. This is operable to write boot code into the programmable memory over the bus. In one embodiment, the above components form a single subsystem within an array of such subsystems. A single control point for the array can transmit updated boot code to the system controller for loading into the programmable memory. This then provides a single interface for simultaneously updating the boot code in all subsystems.

Abstract: In one embodiment, there is provided a method comprising determining a target operating point for an electronic device, the target operating point including a target operating frequency and a target operating voltage; and dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and a current operating voltage to the target operating voltage, wherein during the changing the electronic device is in an active state.

Abstract: A computer system contains selectively available boot block codes. A first boot block is of the conventional type and is stored in storage media such as flash ROM on a system planar with the processor of the computer system. A second boot block is located on a feature card and contains an immutable security code in compliance with the Trusted Computing Platform Alliance (TCPA) specification. The boot block on the feature card is enabled if the first boot block detects the presence of the feature card. The computer system can be readily modified as the computer system is reconfigured, while maintaining compliance with the TCPA specification. A switching mechanism controls which of the boot blocks is to be activated. The feature card is disabled in the event of a computer system reset to prevent access to the TCPA compliant code and function.

Abstract: A method for fast booting an operation system on multiple processors coupled in multi-dimensional array architecture with higher efficiency and reliability. A particular PLEX™ node, which is designated as a primary boot master node, receives a sequence of data packets containing a boot image program to be used to boot the operating system. It first forwards a copy of each data packet to various selected neighboring nodes to which the primary boot master node is directly connected. The nodes that have received the data packets from the primary boot master node further forward the data packets to various other selected nodes, until all the PLEX™ nodes have succeeded in loading the entire boot image program. Three schemes are developed, which improve booting efficiency by allowing all PLEX™ nodes to receive the operating system as close to simultaneously as possible under certain constraints of the way that the PLEX™ nodes are interconnected.

Abstract: An electronic device includes a scanning device for converting one or more configuration symbols on a printed medium into scan data. The scanning device is capable of scanning a configuration sheet and creating the scan data, including the one or more configuration symbols. The electronic device further includes a configuration device that receives the scan data and is capable of extracting the one or more configuration symbols to create one or more corresponding address-independent configuration values. The configuration device is further capable of configuring the electronic device with the one or more address-independent configuration values.

Abstract: An interface circuit includes a frequency divider which divides a frequency of a base clock to provide frequency-divided clock signals; a first address register which stores an address signal at a timing in which the frequency-divided clock signal is turned to high; a second address register which stores the address signal at a timing in which the clock signal is turned to low; a first data register which stores a data signal at a timing in which the clock signal is turned to high; and a second data register which stores the data signal at a timing in which the clock signal is turned to low. The data signals stored in the first and second data registers are selectively outputted.

Abstract: A method, computer program product and system for storing or updating authentications, e.g., passwords, in a boot code image, i.e., binary executable boot code, stored within a Read Only Memory (ROM), e.g., flash ROM, of a terminal from a remote central site. An authentication may be stored in the boot code image in a terminal from a central site by creating a file comprising a boot code image storing the authentication at the central site and then storing the created file in ROM in the terminal. The file may be downloaded from a server at the central site to the terminal. An authentication in the boot code image in a terminal may be updated remotely from a central site by updating the file associated with the boot code image, i.e., updating the authentication, at the central site and then downloading the updated file to the terminal.

Abstract: A data processing system includes a general-purpose data processing unit (PU) including an instruction issuing unit that fetches and decodes an instruction in a program and issues the instruction and an execution unit that executes general-purpose processing according to a general-purpose instruction in the program; a special-purpose data processing unit (VU), including a data path unit for special-purpose data processing, that executes special-purpose data processing according to a special-purpose instruction in the program; and a first clock supply unit for stopping, based on a wait signal that is issued by the VU and shows that the PU is waiting for processing of the VU, a first clock signal for a part of the PU.

Abstract: A technique that is usable with a computer system includes, in response to a startup phase of the computer system in which a system memory of the computer system is not initialized for data storage, detecting a resource of the computer system. Information about the resource reported in response to a second phase of the computer system in which the system memory is initialized.

Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

Abstract: A power supply subsystem for use in a local area network (LAN) includes a direct current (DC) power source, which supplies DC power to at least one of the nodes via at least one of the wire pairs used in communication cabling of the LAN, substantially without interfering with data communications. A signal generator generates a periodic time-varying signal and couples the time-varying signal into the at least one of the wire pairs. A control unit senses a time-varying voltage on the at least one of the wire pairs due to the time-varying signal generated by the signal generator, and responsive to the sensed time-varying voltage, controls the DC power supplied to the at least one of the nodes by the DC power source.

Abstract: A method and apparatus for handling an interrupt from a real-time clock to increment a program clock in a computer system while compensating for missed interrupts due to contention on a system bus from a DMA controller or the like. In accordance with the invention, a count is stored representing a cumulative interval of time that has elapsed without a corresponding incrementing of the program clock. In response to an interrupt from the real-time clock, the processor transfers control to an interrupt handling routine, which determines the interval of time that has elapsed since the previous real-time clock interrupt and increments the cumulative interval of time by the actual interval of time that has elapsed since the previous real-time clock interrupt.

Abstract: An apparatus and method for maintaining a state during a power load change. The apparatus of one embodiment includes a voltage controller coupled to receive a signal from a detector of current change. The detector of current change in this embodiment is coupled to detect change in the current level at a microprocessor and signal a voltage controller of such change, which in turn causes a change in the voltage supplied to the microprocessor. An embodiment of the method comprises using a current detector in detecting current change in a microprocessor, determining according to the current change the power level that is needed to be maintained and increasing the voltage level for a predetermined amount of time to compensate for (any) voltage droop. In an alternative embodiment, a change in power is determined before the change occurs and as such determines the power level needed at the microprocessor.

Abstract: An electronic device includes a scanning device for converting indicia and markings on a printed medium into scan data and a configuration device that receives the scan data. The scanning device is capable of scanning a user-fillable configuration sheet marked by a user of the electronic device and creating the scan data, with the scan data including one or more configuration indicia. The configuration device is capable of decoding the one or more configuration indicia to create one or more corresponding configuration values and configuring the electronic device with the one or more configuration values.

Abstract: A data synchronization system includes a first memory device in a handheld electronic device, a second memory device in a desktop computer, and a synchronization program installed in the desktop computer. The handheld electronic device includes a first data block. The desktop computer includes a second data block. First and second data formats of first and second data stored in the first and second data blocks respectively include a common format section. The first and second memory devices store first and second modification records of the first and second data blocks, respectively. The synchronization program updates the first and second data blocks according to the first and second modification records and transmits only the contents of the common format section when transmitting the first or second data between the handheld electronic device and the desktop computer. A data synchronization method implemented in the system is also disclosed.

Abstract: A method for reducing current consumption of a mobile terminal is provided.

Abstract: This present invention describes a performance control method for a computer. An advanced configuration and power interface (ACPI) is used to control the performance of desktop CPU. According to this method, the control items in the ACPI are set according to the throttling function setting and according to the requirement of the user to set the number of the related performance states supported by the CPU. Then, the operation system selects the related performance state of the CPU according to the required system power.

Abstract: An apparatus, system, method and product for automatically transitioning the physical layer interface of a peripheral device to a low power state when a signal is detected by the communication device on a peripheral bus. The technique may include transitioning to different low power states depending upon whether wake up of the device has been enabled by an operating system.