Abstract: An automatic computer configuration system is disclosed wherein a portable terminal such as a portable telephone set which has been spread widely and is usually carried by a user can be used to automatically configure a computer suitably for a particular user. The automatic computer configuration system comprises a portable terminal and a computer connected to the portable terminal. The portable terminal stores unique computer configuration information to be used for configuration of a computer specified for a particular user. Upon login by a user, the computer communicates with the portable terminal to receive the computer configuration information stored in the portable terminal and automatically configures the computer itself based on the received computer configuration information.

Abstract: When a personal computer system user carries out an OS shutdown, a BIOS does not turn off power, but reboots the system by a software reset to execute a POST, so that the state of the system immediately before starting the launch of the OS after completion of the POST is held in a volatile memory, and the system is shifted to a power saving mode. Subsequently, when the system is booted, the BIOS performs only restoration processing from the power saving mode while omitting the POST execution, and at once launches the OS, thereby shortening the system boot time by omitting the POST execution when the system is booted. Thus, POST processes are performed after the OS shutdown, a state that the POST has been completed after rebooting is held in the volatile memory, and then the system is placed into a state of power saving mode.

Abstract: A data processing apparatus comprises a data processing module, which can be operated in a first operating mode with a normal power consumption and a second operating mode, wherein a power consumption of the data processing module in the second operating mode is smaller than the first power consumption or equal to 0. The data processing apparatus further comprises means for signaling a possibility that the data processing module can be placed into the second operating mode, means for providing a time-varying control signal, means for placing the data processing module from one data operating mode to the other, wherein means for placing is formed to place the data processing module into the other operating mode, when means for signaling signals the possibility and the control signal fulfills a predetermined condition.

Abstract: A method, apparatus, and computer instructions in a data processing system for managing clocks. The functionality of clock sources in the data processing system is verified to identify a set of valid clock sources in response to beginning an initial load process. Hardware is initialized in the data processing system using a valid clock source from the set of valid clock sources.

Abstract: Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

Abstract: A method and system to provide platform-based optimization routines by firmware of a computer system. During a pre-boot phase of a computer system, the firmware identifies one or more hardware devices, such as a central processing unit (CPU) or chipset, of a computer system. The firmware determines an optimized routine library for the one or more hardware devices from a set of optimized routine libraries. The firmware advertises the optimized routine library corresponding to the one or more hardware devices to the computer system for use by an operating system or application. In one embodiment, the firmware of the computer system operates in accordance with the Extensible Firmware Interface (EFI) framework standard.

Abstract: A USB device for performing communications with a second device through a USB interface while supplying electric power to the second device through a power-source supplying line in the USB interface. The USB device includes a communication unit for communicating with the second device, a power source capable of outputting electric power of a voltage being different from a standard power voltage prescribed in the standards of the USB interface. The power source supplies the electric power to the second device through the power-source supplying line. The second device includes a low load unit and a high load unit The power source supplies the electric power having a power voltage higher than the standard power voltage to the high load unit through the power-source supplying line.

Abstract: A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.

Abstract: An information processing unit has a system bus that connects devices configuring the information processing unit. An arbiter performs arbitration related to use of this system bus, and a clock control circuit controls the clock to be supplied to the devices. The clock control circuit can make a bus request to the arbiter and executes a clock switch or clock halt after being granted use of the bus by the arbiter.

Abstract: The specification may disclose a system and related method for control of a server system that may include determining the amount of power delivered in a system utilizing redundant power supplies based on a measurement of the voltage of load share signals between those power supplies, and then allowing additional servers installed in the server system to power-on only if the amount of power required for the combined servers does not exceed the maximum available power or exceed the power required for a certain type of redundant power supply operation.

Abstract: When controlling a clock to a central processing unit, it is naturally preferable not to change existing circuits which are not related to the control of the clock. A clock control circuit inputs a clock input CLK, and generates a clock output CLKOUT for the central processing unit. In the clock control circuit, CLK is masked by a write operation to an internal register. CLKOUT is stopped by the mask operation. The mask operation is carefully designed to be initiated when the internal cycle of the central processing unit is detected. The resumption of the clock is initiated by interrupts.

Abstract: The invention provides a power control device for a computing unit, which is optimal for saving power. When MPEG data is supplied, a CPU starts decoding the MPEG data. The MPEG data is decoded by independently decoding video data and music data. When decoding the MPEG data, in each operation unit included in the MPEG data, the clock frequency of the CPU can be adjusted so as to reduce the power consumption of the CPU on the basis of the data length of the operation unit for a period during which the CPU performs an operation on the data in the operation unit.

Abstract: A distributed power management system for a bus architecture or similar communications network. The system supports multiple low power states and defines entry and exit procedures for maximizing energy savings and communication speed.

Abstract: A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port.

Abstract: Power control signals for main power and RAM power are utilized to determine when the system is in the suspend to RAM state. Once the system is determined to be in the suspend to RAM state state, a control circuit detects peripheral activity, such as activity of a mouse or a keyboard, and generate a wake-up signal.

Abstract: A high-speed programmable serial port having a finite state machine, a clock generator capable of controlling shifting of bits from a shift register and a shift register having a bit counter capable of maintaining a numbered count of data bits in a serial output. The clock generator and shift register reduce the burdens on a finite state machine, thus improving data throughput and the ability to provided data according to a multitude of data protocols.

Abstract: Methods and apparatus to modify alternate storage are disclosed. In an example, a method includes receiving an interface from a device in the pre-boot environment, wherein the interface identifies a location of the device and a location of alternate storage on the device and receiving a request for modification of the alternate storage of the device. The example method may also include receiving modification data to be written into the alternate storage of the device and writing the modification data to the alternate storage of the device using the interface in the pre-boot environment.

Abstract: A memory system that includes a plurality of memory devices includes: a controller for outputting a first clock signal, a second signal and a plurality of command/address input signals corresponding to the plurality of memory devices, respectively; and a register and delay circuit unit for outputting command/address output signals after receiving the command/address input signals front the controller and then correcting transmission delay due to transmission lines; wherein the plurality of memory devices receive the command/address output signals from the register and delay circuit unit via the transmission lines, respectively, and sample the command/address output signals using the first clock signal directly inputted from the controller. As a result, the memory system can simplify the layout of semiconductor device design and prevent the collision of clocks.

Abstract: A detector detects information about a firmware system. The detector includes an interface that receives a generic instruction. The generic instruction may be a function call made through an EFI shell. The detector has a controller communicatively connected to the interface. The controller receives the generic instruction and gathers information about the firmware system. Gathering information about the firmware system permits platform-specific firmware system functions to be written to the firmware system. The controller gathers information about the firmware system by accessing a data-gathering function based on the generic instruction. The controller retrieves the information through the data-gathering function and transfers the information to the interface.

Abstract: A panel device mounted on a computer case comprises an adjustment unit for adjusting CPU's operating frequency, a display module for showing system information, and a microprocessor which interconnects the adjustment unit and the display module with the computer system. The microprocessor can perform adjustment done by the adjustment unit and issue a service request signal to the computer. In response, the computer issues signals about system information to the microprocessor for being processed and showed on the display module.