Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist residue in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist residue, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.

Abstract: The present disclosure relates to an array substrate, a method of fabricating the same, and a display panel. The array substrate includes a conductive layer formed on the base substrate, a dielectric layer formed on the conductive layer, wherein the dielectric layer has an opening exposing the conductive layer, wherein a vertical projection of the opening on the base substrate is in at least a portion of the pixel spacing region, a first electrode formed on the dielectric layer, a luminescent layer having a first portion on the first electrode and a second portion on the conductive layer in the opening, a second electrode formed on the luminescent layer, and an electrical connection portion in the second portion of the luminescent layer for providing an electrical connection from the conductive layer to the second electrode, and wherein the electrical connection portion is more conductive than the luminescent layer.

Abstract: A method of forming patterns of a semiconductor device includes forming a photoresist pattern, which contains a first carbon compound, on a substrate, reforming a top surface of the photoresist pattern to form an upper mask layer which contains a second carbon compound, different from the first carbon compound, on the photoresist pattern, and etching a portion of the substrate using the upper mask layer and the photoresist pattern as an etch mask.

Abstract: A technique that recovers from degradation in crystalline nature in an ion-implanted region is provided. A method of manufacturing a semiconductor device, includes: an ion implantation step of ion-implanting p-type impurities by a cumulative dose D into an n-type semiconductor layer containing n-type impurities; and a thermal annealing step of annealing an ion-implanted region of the n-type semiconductor layer where the p-type impurities are ion-implanted, in an atmosphere containing nitrogen, at a temperature T for a time t, wherein the cumulative dose D, the temperature T, and the time t satisfy a predetermined relationship.

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, and bit lines overlying the memory stack structures. Vertical discharge transistors are provided, each of which includes a respective vertical discharge transistor channel that extends through a second alternating stack of second insulating layers and second electrically conductive layers laterally spaced from the first alternating stack.

Abstract: A method of manufacturing a semiconductor package includes obtaining a plurality of individual chips classified according to a test bin item as a result of performing an electrical die sorting (EDS) process including testing electrical characteristics of a plurality of chips at a wafer level, packaging the individual chips on corresponding chip mounting regions of a circuit substrate and forming a plurality of individual packages based on position information of the chip mounting regions, each of the individual packages having test bin item information corresponding to the test bin item, classifying the plurality of individual packages according to the test bin item based on the test bin item information, and testing the individual packages classified according to the test bin item.

Abstract: An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

Abstract: A silicon carbide chip array containing a silicon carbide substrate; a silicon carbide layer on top of the silicon carbide substrate; a first metal contact connected to the silicon carbide substrate; and two second metal contacts connected to the first portion and the second portion respectively. The silicon carbide layer is thinner and having lower doping than the silicon carbide layer. The silicon carbide layer includes a first portion and a second portion which are separate from each other. Each one of the second metal contacts forms a semiconductor device with the first metal contact. At least one of the first and second portions contains a side face which is inclined with respect to the silicon carbide substrate. Such a configuration enhances the breakdown voltage and reduces leakage current of the resultant silicon carbide diode array.

Abstract: This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method may include: providing a top wafer structure, where the top wafer structure includes a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, where the bottom wafer structure includes a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad, to form multiple pads. This application may mitigate a problem that bonded pads are connected to each other.

Abstract: There is provided a bonding method capable of accurately positioning a bonding stage. According to an aspect of the present invention, a bonding method using a bonding apparatus including a rotation drive mechanism for rotating a bonding stage 1 about a ?-axis includes the steps of: (e) locking the bonding stage with respect to the ?-axis, and bonding a wire or bump onto a certain area of a substrate held on the bonding stage; (f) unlocking the bonding stage with respect to the ?-axis, and rotating the bonding stage about the ?-axis with the rotation drive mechanism; and (g) locking the bonding stage with respect to the ?-axis, and bonding a wire or bump onto a remaining region of the substrate.

Abstract: In one embodiment, a semiconductor device is provided with a semiconductor layer made of a nitride semiconductor, a first gate electrode, a first structure body between the first gate electrode and the semiconductor layer, and a first insulating layer between the semiconductor layer and the first structure body. The first structure body has a first intermediate layer made of a conductor to suppress generation of charges at respective interfaces with adjacent layers, a first layer having dielectric property between the first gate electrode and the first intermediate layer, and a second layer having dielectric property between the first gate electrode and the first layer, and has dipoles at an interface between the first layer and the second layer.

Abstract: A method to reduce the number and type of processing steps to achieve conductive lines in the planes of a substrate concurrently interconnecting conductor through the substrate, by forming structures in the planes of a substrate. These structures may include interconnect lines, bond pads, and other structures, and improve the performance of subsequent unique processing while simultaneously reducing the manufacturing complexity to reduce time and cost. These structures are formed by selective etching using chemical mechanical polishing, and then completed using a single fill step with a conductive material.

Abstract: A light emitting device includes a substrate and a light emitting layer over the substrate, the light emitting layer. The light emitting layer has a light emitting pixel array including a plurality of light emitting pixels and a spacer. The spacer is configured to separating the plurality of light emitting pixels. Each light emitting pixel has a light emitting material and an electrode between the light emitting material and the substrate. The spacer has a bump having a curved surface extruding away from the substrate, and the bump covers a peripheral region of the electrode.

Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.

Abstract: A package to die connection system and method are provided. The system includes a semiconductor device having a substrate with a top surface. A gasket is affixed to the top surface of the substrate and has at least one cavity with a portion of the cavity open to a sidewall of the gasket. A semiconductor die is attached to the top surface of the substrate. A sidewall of the semiconductor die is abutted with the sidewall of the gasket. A portion of a metal layer is exposed to the open portion of the cavity. A pillar located in the cavity is electrically connected to the exposed portion of the metal layer.

Abstract: Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.

Abstract: A semiconductor device is provide. The device includes a first n? type of layer, a second n? type of layer, and an n+ type of region sequentially disposed on a first surface of a substrate. A trench is disposed on a side surface of the second n? type of layer, a p type of region is disposed between the second n? type of layer and the trench, and a gate electrode is disposed on a bottom surface of the trench. A source electrode is disposed on the n+ type of region and a drain electrode is disposed on a second surface of the substrate. The second n? type of layer includes a first concentration layer, a second concentration layer, a third concentration layer, and a fourth concentration layer sequentially disposed on the first n? type of layer.

Abstract: A vertical memory device includes first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate, a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region, a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction, and a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel. The channel directly contacts a sidewall of the second impurity region.

Abstract: A method for preparing a light emitting diode chip, the method including: 1) providing a substrate; 2) growing an n-type semiconductor layer, an active layer and a p-type semiconductor layer on the substrate sequentially in that order; 3) forming a step including an upper horizontal end surface, a lower horizontal end surface and a step surface in the n-type semiconductor layer, the active layer and the p-type semiconductor layer; 4) growing a transparent conductive layer on the upper horizontal end surface, and forming an etching hole in the middle of the transparent conductive layer; 5) forming an N electrode on the lower horizontal end surface, and forming a P electrode in the etching hole; 6) growing a metal catalyst layer on the light emitting diode chip; and 7) forming a fluorinated graphene protective layer on the metal catalyst layer.