Abstract: A method for manufacturing a silicon epitaxial wafer includes: preparing a test silicon wafer in advance, forming the multilayer film on a surface of the test silicon wafer, and measuring a warp direction and a warp amount (Warp) W of the silicon wafer having the multilayer film formed thereon; and selecting a silicon wafer as a device formation substrate and conditions for forming an epitaxial layer which is formed on the silicon wafer as the device formation substrate in such a manner that a warp which cancels out the measured warp amount W is formed in a direction opposite to the measured warp direction, and forming the epitaxial layer on a surface of the selected silicon wafer as the device formation substrate where the multilayer film is formed under the selected conditions for forming the epitaxial layer.

Abstract: A method to reduce the number and type of processing steps to achieve conductive lines in the planes of a substrate concurrently interconnecting conductor through the substrate, by forming structures in the planes of a substrate. These structures may include interconnect lines, bond pads, and other structures, and improve the performance of subsequent unique processing while simultaneously reducing the manufacturing complexity to reduce time and cost. These structures are formed by selective etching using chemical mechanical polishing, and then completed using a single fill step with a conductive material.

Abstract: An embodiment is MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.

Abstract: A method for producing a planar free surface comprising embedded, contactable nanostructures includes arranging at least one nanostructure on a surface of an initial substrate; applying a first layer to the surface of the initial substrate, wherein the first layer embeds the at least one nanostructure; applying a target substrate to the first layer; and separating the initial substrate from the first layer such that the at least one nanostructure embedded in the first layer has a planar free surface. An additional layer is applied to the surface of the initial substrate before the at least one nanostructure is applied to the initial substrate, and in that the initial substrate is removed from the first layer using a solvent.

Abstract: A method of fabricating semiconductor packages includes forming an insulating polymer layer on a substrate to cover a plurality of conductive patterns on the substrate, planarizing the insulating polymer layer by pressing the insulating polymer layer downward by using at least one pressure member, and patterning the planarized insulating polymer layer to expose at least parts of the plurality of conductive patterns.

Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.

Abstract: An organic semiconductor transistor is provided. The organic semiconductor transistor includes a gate electrode, a gate insulating layer positioned on the gate electrode, a source electrode and a drain electrode which are positioned on the gate insulating layer and spaced apart from each other, a channel layer formed of an organic semiconductor on the gate insulating layer on which the source electrode and the drain electrode are formed, and a dopant layer formed by injecting dopant molecules downward from an upper portion of the channel layer, wherein the dopant layer is formed to be spaced above a position at which each of the source electrode and the drain electrode is in contact with the channel layer, and the dopant molecules and the organic semiconductor form a material combination in which the dopant molecules diffuse in the organic semiconductor in a solid-state diffusion manner.

Abstract: A semiconductor device includes an insulator on a substrate and having opposite first and second sides that each extend along a first direction, a first fin pattern extending from a third side of the insulator along the first direction, a second fin pattern extending from a fourth side of the insulator along the first direction, and a first gate structure extending from the first side of the insulator along a second direction transverse to the first direction. The device further includes a second gate structure extending from the second side of the insulator along the second direction, a third fin pattern overlapped by the first gate structure, spaced apart from the first side of the insulator, and extending along the first direction, and a fourth fin pattern which overlaps the second gate structure, is spaced apart from the second side, and extends in the direction in which the second side extends.

Abstract: In various embodiments, light-emitting devices incorporate graded layers with compositional offsets at one or both end points of the graded layer to promote formation of two-dimensional carrier gases and polarization doping, thereby enhancing device performance.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

Abstract: A method of manufacturing an organic semiconductor transistor is provided. The method incudes forming a gate insulating layer on a gate electrode, forming a source electrode and a drain electrode which are spaced apart from each other on the gate insulating layer, forming a channel layer using an organic semiconductor on a gate insulating layer on which the source electrode and the drain electrode are formed, and thermally depositing dopant molecules on the channel layer, wherein, in the thermal deposition of the dopants, the dopant molecules are thermally deposited to be spaced above a position at which each of the source electrode and the drain electrode is in contact with the channel layer, and the dopant molecules and the organic semiconductor form a material combination in which the dopant molecules diffuse in the organic semiconductor in a solid-state diffusion manner.

Abstract: A method of manufacturing a semiconductor element includes forming a first silicon oxide film on a semiconductor wafer under a first film forming condition; forming a second silicon oxide film on the first silicon oxide film under a second film forming condition, a density of the second silicon oxide film being lower than a density of the first silicon oxide film; coating, with a photoresist, a region including the second silicon oxide film; exposing the photoresist using a photomask having an aperture and being disposed such that at least a portion of an edge of the aperture is disposed on the second silicon oxide film; removing a portion of the photoresist to form a photoresist pattern that has an overhang shape in a cross-section of the photoresist pattern; forming an electrode film on a region including the photoresist pattern; and performing lift-off by removing the photoresist pattern.

Abstract: A method for forming a trench diode for a power semiconductor device includes forming a first trench having a first opening and a second trench having a second opening in a substrate material, the second opening of the second trench being wider than the first opening of the first trench. An insulating layer is formed over surfaces of the first and second trenches. A first semiconductor material is provided within the first and second trenches, the first semiconductor material filling the first trench at least until the first opening is entirely plugged and partially filling the second trench so that a portion of the second opening remains open, the first semiconductor material having a first conductivity type. A second semiconductor material is provided within the second trench and over the first semiconductor material, the second semiconductor material having a second conductivity type that is different from the first conductivity type.

Abstract: A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.

Abstract: A semiconductor die is disclosed upon which is formed direct current (DC) isolated first and second circuits. The first circuit is configured for electrical connection to a first ground. The second circuit is configured for electrical connection to a second ground. The first and second grounds can be at different potentials. The first and second circuits were formed using front end of line (FEOL) and back end of line (BEOL) processes. The first circuit includes a plurality of first devices, such as transistors, which were formed during the FEOL process, and the second circuit includes only second devices, such as transistors, which were formed during the BEOL process.

Abstract: Multiple degenerately-doped silicon layers are implemented within resonant structures to control multiple orders of temperature coefficients of frequency.

Abstract: Package structures and methods of forming the same are disclosed. One of the package structures includes a first die, a second die, a dummy substrate and an encapsulant. A bottom surface of the second die is adhered to a top surface of the dummy substrate through a glue layer, and a total area of the bottom surface of the second die is different from a total area of the top surface of the dummy substrate. A total thickness of the first die is substantially equal to a total thickness of the second die, the dummy substrate and the glue layer. The encapsulant is disposed aside the first die, the second die and the dummy substrate.

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer; forming a cap layer on the bottom electrode layer; and removing part of the cap layer, part of the bottom electrode layer, and part of the IMD layer to form a trench.

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

Abstract: A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer.