Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains.

Abstract: A solid-state imaging device of the invention is provided with a CCD-structured branching unit which selects one signal charge sensor having characteristics suitable for the conditions of use from among a plurality of signal charge sensors each having different characteristics and forms a signal charge transmission path leading from the horizontal CCD to the selected signal charge sensor. As a result, there is no need to switch over the external circuit of the solid-state imaging device according to the conditions of use, which makes it possible to hold down the cost and reduce the size of the external size.

Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).

Abstract: Disclosed is a floating gate EPROM cell wherein a trench is formed in and divides the semiconductor substrate into two portions. Separated source and drain regions are formed in one portion and contact one side of the trench region, and a control gate region is formed in the second portion and contacts the opposite side of the trench. A first insulating film covers the source, drain, trench regions and part of the control gate region, a portion of which is covered by a first polycrystalline silicon film which forms the floating gate. A second insulating layer covers the first polycrystalline silicon film and also a portion of the control gate region, which, in turn, is covered by a second polycrystalline silicon layer which extends beyond the second insulating layer into electrical contact with the control gate region. Thus, a control gate is provided both above and below the floating gate.

Abstract: In a CCD device, a plurality of trench holes are formed in high resistivity semiconductor layer and juxtaposed in a charge transfer direction, and charge transfer electrodes are buried in the trench holes. Charge transfer regions are formed in the semiconductor layer around the vicinity of the respective trench holes during a main operating state.

Abstract: A semiconductor integrated circuit device is provided which include a plurality of cell columns each having a number of unit cells previously fabricated on a semiconductor substrate selected from the plural kinds of unit cells which are formed in desired circuits by electrically connecting circuit devices previously arranged. Each column includes at least one kind of unit cell of a dynamic circuit which has a node in a floating state during the operation of the cell unit. A fixed potential shield layer is also provided on the cell columns so as to cover the nodes of the dynamic circuits. By virtue of this, a wiring area for electrically connecting the desired cell units can be located between the cell columns and above the shield layer. In other words, signal wirings in the wiring area can pass over the nodes of the dynamic circuits. without adverse parasitic effects. The unit cell can also be provided with a precharge circuit comprising a standard cell and an in-cell wiring layer.

Abstract: A novel light emitting semiconductor device is disclosed. The device utilizes real space transfer (RST) of carriers, and comprises regions of opposite conductivity type separated by a barrier layer. The first region (termed the "emitter") comprises at least two contacts. Application of appropriate bias between the two contacts and between the emitter and the second region results in injection of hot carriers into the second region, resulting in luminescence in the second region. The invention can be embodied in coherent as well as incoherent light sources. A preferred embodiment is a vertical cavity surface emitting laser. The device can serve as a novel logic element that has electrical inputs and an optical output, and provides a non-trivial logic function.

Abstract: A charge-coupled device includes a parallel section of parallel channels which are situated next to one another and are mutually separated by limitation zones, and a single readout register coupled thereto. The readout register is provided with clock electrodes in a multi-layer wiring system, the electrodes of the upper layer belonging to a common phase and being constructed as a continuous track which extends over the other electrodes. In the bottom wiring layer, electrodes are formed which are each associated with a limitation zone between the parallel channels and which have a length which is at most equal to the width of the limitation zones, and which also belong to a common phase, so that narrow-channel effects are avoided. The invention is of particular importance for CCD image sensors.

Abstract: A photosensitive device includes a semiconductor body (1) having a first region (2) of one conductivity type adjacent a given surface (3) of the body with a second region (4) of the opposite conductivity type surrounding the first region (2) so as to form with the first region a main pn junction (5) terminating at the given surface (3), the main pn junction (5) being reverse-biassed in operation of the device. One or more further regions (6) of the one conductivity type surround the main pn junction (5) adjacent the given surface (3) so that each further region (6) forms a photosensitive pn junction (17) with the second region (4), the further region(s) (6) lying within the spread of the depletion region of the main pn junction (5) when the main pn junction (5) is reverse-biassed in operation of the device so as to increase the breakdown voltage of the main pn junction (5).

Abstract: A plastic mold semiconductor device comprises a semiconductor chip; a die pad which is made of a thin metallic plate for supporting the semiconductor chip; leads which surround the die pad, wires for connecting electrodes on top of the semiconductor chip and the leads; and plastic mold for sealing the entire device; the die pad being comprised of support sections separated by a fixed gap from a sub-element interconnecting member which is insulated from the semiconductor chip, and connection between the power source or signal related lead and the electrode which is on top the semiconductor chip and is located from the power source or signal related lead is connected by the sub-element interconnecting member.

Abstract: When bypassing a high voltage surge by externally installing a diode between a collector and a gate and protecting a circuit by turning on an IGBT, it is difficult to select a withstand voltage of the diode, because the withstand voltage of the IGBT must be higher with a certain margin. In the present invention, regions of an inverse conductivity type are formed in a high resistivity layer of an IGBT as in base region, and a transistor is formed together with a collector layer of an inverse conductivity type, which is connected between the collectors of an IGBT to be utilized as a clamping transistor. The breakdown voltage of this transistor is made lower than the breakdown voltage of a bipolar transistor of the IGBT main body. Then when the transistor breaks down, the gate-emitter capacity of the IGBT is charged and the IGBT is turned on, thus absorbing the high energy produced by an abnormal voltage into the chip and increasing the withstand capacity.

Abstract: A charge coupled device (CCD) has a charge storage region and a potential barrier region. The CCD includes a first layer made of a first conductivity type semiconductor, a second layer made of a second conductivity type semiconductor and provided on the first layer, where the first and second conductivity types are mutually opposite types selected from n-type and p-type semiconductors, a third layer made of a first conductivity type semiconductor, impurity diffusion regions provided in at least a surface part of the third layer and having an impurity density higher than that of the third layer, a first gate electrode provided on the third layer between two mutually adjacent impurity diffusion regions, and a second gate electrode provided on each impurity diffusion region of the third layer. The impurity diffusion region forms the charge storage region of the CCD and the third layer between the two mutually adjacent impurity diffusion regions forms the potential barrier region of the CCD.

Abstract: In a large-area controlled-turn-off high-power semiconductor component containing a multiplicity of finely structured individual components, a semiconductor device (12) is formed by a multiplicity of small-area semiconductor chips (7) which are accommodated alongside one another in a common housing (13) and connected in parallel. This achievement avoids problems of yield with structures which are becoming finer.

Abstract: A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by independent gate electrodes (13, 15) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a drain electrode (21). Each channel is also coupled to a source electrode (25-26). The quantum well channels (12, 14, 16) and quantum well gates (13, 15) are separated from each other by barrier layers (18) of a wide bandgap semiconductor material.

Abstract: A monolithic vertical-type semiconductor power device comprises an N+ type substrate 1 over which there is superimposed an N- type epitaxial layer 2 in which there is obtained a P type isolation pocket 3. The pocket 3 contains N type regions 4, 15 and P type regions 6 which in turn contain N+ type regions 11, 12 and P type regions 7, 9, 10 which define circuit components of the device. Isolation pocket 3 is wholly covered by a first metallisation 21 connect to ground. The metallisation 21 is in turn protected by a layer of insulating material 18 suitable for allowing the crossing of metal tracks or of a second metallisation for the connection of the different components.

Abstract: An improved junction type photovoltaic element, characterized by having an organic semiconductor layer formed of a polysilane compound of 6000 to 200000 in weight average molecular weight which is represented by the following general formula (I): ##STR1## Wherein, R.sub.1 stands for an albyl group of 1 to 2 carbon atoms; R.sub.2 stands for an alkyl group, cycloalkyl group, aryl group or aralkyl group of 3 to 8 carbon atoms; R.sub.3 stands for an alkyl group of 1 to 4 carbon atoms; R.sub.4 stands for an alkyl group of 1 to 4 carbon atoms; A and A' respectively stands for an alkyl group, cycloalkyl group, aryl group or aralkyl group of 4 to 12 carbon atoms wherein the two substituents may be the same or different one from the other; and each of n and m is a mole ratio showing the proportion of the number of respective monomers versus the total of the monomers in the polymer wherein n+m=1, 0<n.ltoreq.1 and 0.ltoreq.m<1.

Abstract: A thermoelectric sensor element that is adapted to respond to thermal radiation is capable of manufacture into a sensor array on a single crystal semiconductor means, such as silicon. An anisotropically etched pit is provided under the sensing surface, and the pit generally corresponds to the geometry of the sensor element. The geometry is selected to be rectangular and falls along a selected orientation of the particular crystalline structure used for manufacture of the device to thereby allow for a high density of the sensor elements. The sensor elements are manufactured of two dissimilar metals in a sinuous pattern to provide the thermoelectric effect.

Abstract: A sensor element that is adapted to respond to radiation, and which is adapted to the manufacture of a sensor array is manufactured into a single crystal semiconductor means such as silicon. An anisotropically etched pit is provided under the sensing surface, and the pit generally corresponds to the geometry of the sensor element. The geometry is selected to be rectangular and falls along a selected orientation of the particular crystalline structure used for manufacture of the device to thereby allow a high density of sensor elements to provide an efficient array.

Abstract: An integrated circuit has a silicon mesa disposed on a substrate and a field insulator structure in proximity to the mesa and having an opening over a top mesa surface. The opening, which exposes sidewalls in the structure, is positioned with respect to the mesa and has dimensions such that the structure is disposed to overlap a region of the mesa along an outer mesa periphery. A layer of polysilicon extends along a top surface of the structure and into the opening and adjacent to the mesa top surface. An insulator is disposed between the poly layer and the mesa top surface, the insulator having a layer of thermal gate oxide disposed adjacent to the poly layer and having a layer of pyrogenic oxide disposed between the thermal gate oxide layer and the mesa top surface.

Abstract: A semiconductor device package is disclosed which facilitates the dissipation of heat generated by the enclosed semiconductor device. The package comprises a housing apparatus having a plurality of portions, a holding apparatus having a semiconductor device thermally attached, a thermal path formed within at least one of the portions of the housing apparatus, and a thermally conductive connection for thermally connecting the holding apparatus to the thermal path. The portions of the housing apparatus join together to form an enclosed chamber which encases the holding apparatus, the semiconductor device, and the thermally conductive connection. The thermal path thermally connects the interior of the package to the external environment. By thermally connecting the holding apparatus to the thermal path formed within the housing apparatus, a direct thermal path is created between the device and the external environment so that heat from the device may readily escape from the interior of the package.