Abstract: A semiconductor device includes a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) re smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resin film in patterning the conductive interconnection layer.

Abstract: A novel concept and structure of a semiconductor circuit are disclosed which utilize the fact that the interaction between the carriers such as electrons and holes supplied in a meso-scopic region and the potential field formed in the meso-scopic region leads to such effects as quantum interference and resonance, with the result that the output intensity is changed.

Abstract: A conductor attachment wherein each conductor is mounted on a dielectric tape and has an attachment portion that is supported by the tape to an adjacent location a uniform distance from the bonding location and that contacts on a level with the plane of the underside of the tape. One conductor supporting tape has portions of the tape that extend into a central contacting area opening to contact locations at contacting pads in rows remote from the edge. Another supporting tape has window openings at the contacting locations. The conductor ends are brought into the level of the underside of the tape by a manufacturing rolling operation between an elastomer surface roller and a solid backing roller.

Abstract: A liquid crystal element has a pair of opposed substrates, electrodes thereon, and a ferroelectric liquid crystal sealed between the substrates. A film of a conductive organic compound or a mixture of a conductive organic compound and another organic compound is disposed on the substrate surface, optionally via an orienting film. The conductive organic compound is typically a charge-transfer complex. The film may be formed by an LB method, coating, vapor phase polymerization or electrolytic polymerization. The element has improved optical bistability, contrast, and response.

Abstract: A semiconductor device is made by etching a III-V compound semiconductor layer having a (100) surface using a mask having an opening defined by edges including at least one edge along an [011] direction of the layer so that the surface revealed by etching has a (111) orientation. An electrode is formed on the (111) surface by vacuum vapor deposition.

Abstract: A field-effect, power-MOS transistor wherein a region under the gate contact pad is specially doped with a dopant that is electrically compatible with that in the transistor's channel to obviate problems of electrical breakdown in that region.

Abstract: In a semiconductor integrated circuit, a digital circuit section and an analog circuit section are formed on a substrate. A pair of first power source lines connects a circuit element in the digital circuit section to a power source, while a pair of second power source lines connects a substrate region in the digital circuit section to the power source. The pair of second power source lines is formed separately from the pair of first power source lines in the digital circuit section. The substrate region in the digital circuit section is surrounded by a guard ring well, to which one of the pair of second power source lines is connected.

Abstract: A ceramic semiconductor package has a ceramic bridge to provide shorter bond wire lengths and other interconnections for the semiconductor device.

Abstract: An electromechanical sensor is provided which comprises an n-type semiconductor region which defines a flexible member surrounded by a thicker base portion; at least one piezoresistor formed in the semiconductor region; an n+ region formed in the thicker base portion; a first insulative layer which overlays the piezoresistor and which extends at least from the piezoresistor to the first n+ doped region; a guard layer which overlays at least a portion of the first insulative layer such that the guard layer overlays the piezoresistor and extends at least from the piezoresistor to a point adjacent to the n+ region; and a first bias contact which electrically interconnects the n+ region and the guard layer.

Abstract: An organic thin film and process for making the same, having electroconductivity, semiconductivity or superconductivity. The film is made of vapor-deposited bisethylenedithiatetrathiafulvalene (BEDT-TTF) by heating BEDT-TTF at a pressure of 10.sup.-2 Torr or below and at a temperature not higher than 260.degree. C. The temperature of the substrate on which the vapor is deposited is held at a lower temperature than the vapor. A thin film produced under these temperature and pressure conditions contains substantially no decomposition product. The electroconductivity of the film can be adjusted by selecting the substrate used for vapor-deposition of the film and the electron acceptor used as a dopant of the film. In order to achieve a vapor-deposited film with a high degree of orientation, silicon wafer is preferably used as a substrate for the film.

Abstract: A TFT is formed on a transparent insulative substrate, and includes a gate electrode, a gate insulating film, a semiconductor film which has a channel portion, source and drain electrodes. An insulating film is formed on the TFT so as to cover at least the drain electrode and the gate insulating film. A transparent electrode is formed on at least part of insulating film except for a portion above the channel portion on the semiconductor film. The transparent electrode is electrically connected to the source electrode via a through hole which is formed on the insulating film at a position of the source electrode.

Abstract: vertical power MOSFET which comprises a semiconductive substrate of a first conductivity type serving as drain, an impurity region of a second conductivity type on a part of the surface of the semiconductive substrate, an impurity region of a first conductivity type formed on a part of the surface of the second conductivity type impurity region and serving as source, and a surface portion of a second conductivity type semiconductive substrate between source and drain serving as a channel portion with a gate electrode thereon through an insulating film, so that voltage is applied to the gate electrode to control channel current between source and drain, wherein the first conductivity type semiconductive substrate comprises a low resistivity layer and a high resistivity layer epitaxially formed on the low resistivity layer, and at an interface between the low resistivity layer and the high resistivity layer is provided a convexed portion which projects at least to the high resistivity layer side.

Abstract: A solid-state memory unit is constructed using stacked wafers containing a large number of memory units in each wafer. Vertical connections between wafers are created using bumps at the contact points and metal in through-holes aligned with the bumps. The bumps on one wafer make contact with metal pads on a mating wafer. Mechanical bonding between the bumps and mating metal pads on another wafer is preferably avoided so that fractures due to thermal expansion differentials will be prevented. Serial addressing and data access is employed for the memory units to minimize the number of connections needed. Also, the metal pads, through-holes and bumps are formed at corners of the die and thus shared with adjacent units whenever possible, further reducing the number of vertical connections.

Abstract: The present invention is to provide a CCD delay line in which a deterioration of a charge transfer efficiency can be reduced by maintaining a charge amount treated in a charge transfer section provided at the rear stage of an intermediate output section. According to an aspect of the present invention, in a charge transfer device having charge transfer sections of a plurality of stages consisting of electrode pairs of a transfer gate electrode and a storage gate electrode and at least one intermediate output section provided at the rear stage of a charge transfer section of a predetermined stage from the signal input side, a cross-sectional area of at least one of the transfer gate electrode and the storage gate electrode in the charge transfer section provided at the rear stage of the intermediate output section is selected to be larger than that in the charge transfer section provided at the front stage of the intermediate output section.

Abstract: Each diode of an indium antimonide electro-optical detector array on a dielectric backing transparent to optical energy to be detected includes a junction that less than about a half micron from the diode surface on which the energy is initially incident. The optical energy is incident on a P-type doped region prior to being incident on a bulk N-type doped region. Both P- and N-type doped regions of adjacent diodes are spaced from each other. Metal electrically connects the P-type doped regions together without interfering substantially with the incident optical energy. A multiplexer integrated circuit substrate extends parallel to the backing and includes an array of elements for selective readout of the electric property of the diodes. The elements and diodes have approximately the same topographical arrangement so that corresponding ones of the elements and diodes are aligned. An array of indium columns or bumps connects the corresponding aligned elements and diodes.

Abstract: A lead over chip packaged device that is less prone to package cracking during surface mounting is disclosed. The lead over chip lead frame overlies the active face of a semiconductor circuit. The backside of the semiconductor circuit is covered with an aminopropyltriethoxysilane coating. The aminopropyltriethoxysilane coating promotes adhesion between the backside of the semiconductor circuit and the mold compound used to encapsulate the device. This reduces package cracking resulting from delamination between the inactive face of the chip and the mold compound during reflow solder.

Abstract: A semiconductor thyristor of the Static Induction type having a split-gate structure, e.g., driving gates and non-driving gates, for controlling cathode-anode current flow. The split-gate structure comprises a plurality of primary driving gates formed in recesses of the channel region which respond to an external control signal for providing primary current control, and a plurality of secondary non-driving gates which are influenced by electric fields in the channel region extant during thyristor operation for providing secondary current control. In operation, the driving and non-driving gates coact so that the non-driving gates, having an induced potential lower than the potential applied to the driving gates, absorb charge carriers injected in the channel during thyristor operation.

Abstract: At least part of a low impurity concentration collector region which lies between the emitter and collector regions of a bipolar transistor in a Bi-CMOS device is formed to have a low impurity concentration. Therefore, a high emitter-collector withstanding voltage can be obtained. Further, at least part of the low impurity concentration collector region which lies between the base region and an opposite conductivity type region is formed to have a high impurity concentration. Therefore, the punch-through withstanding voltage of a parasitic transistor formed of the base, collector and, opposite conductivity type region can be enhanced, and, at the same time, the collector resistance can be reduced.

Abstract: A metallic or ceramic dam structure surrounding a semiconductor die in a semiconductor device assembly is disclosed. The dam structure forms a cavity containing a potting compound encapsulating the die. The dam structure may also be provided with a flat lid portion, enclosing the cavity and forming a flat, exterior, heat-dissipating surface for the semiconductor device assembly. Further, an additional add-on structure, having heat dissipating fins, may be joined to the dam structure, exterior the semiconductor device assembly, to provide additional heat dissipation. The add-on structure is particularly well-suited to applications where air cooling is available.

Abstract: A one-dimensional time-delay integration solid-state imager includes a plurality of light-to-electricity conversion parts which store signal charges generated in response to incident light, a vertical CCD corresponding to a series of the light-to-electricity conversion parts for transferring stored signal charges, and a gate for controlling transfer of signal charges stored at the light-to-electricity conversion parts to the vertical CCD. The signal charges corresponding to the same observed image moving on the plurality of light-to-electricity conversion parts are added to enhance the signal-to-noise ratio, and a background signal charge removing region for removing background signal charges is provided at the vertical CCD for removing background charges during the transfer of signal charges.