Abstract: A layout of a MOSFET current driver is disclosed which improves the fabrication yield and the current drive capability over that of the prior art while keeping the layout area the same as the prior art. In this design, the gate is laid out to have a lateral serpentine pattern rather than a vertical serpentine pattern to create a larger gate in order to improve the current drive capability. In addition, the contacts for the drain and the contacts for the source are removed from the gate layout area which facilitates condensing the gate layout and increasing the size of the gate. Also, this design has only two metal strips: one for the drain and one for the source of the MOSFET current driver. The two metal strips substantially overlap the serpentine patterned gate. Having only two metal strips reduces the spaces between the metal strips to one space thereby reducing the probability of having a short or a defect and improving the fabrication yield.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: A MOS-type semiconductor integrated circuit device is provided in which MOS transistors are formed in a vertical configuration. The MOS transistors are constituted by pillar layers formed on the substrate. The outer circumferential surfaces of the pillar layers are utilized to form the gates of the MOS transistors. Thus, large gate widths thereof can be obtained within a small area. As a result, the total chip area of the MOS transistors can be significantly reduced while maintaining a prescribed current-carrying capacity.

Abstract: A fuse link includes a fuse portion and a exothermic charge adjacent the fuse portion for blowing the fuse portion upon application of a triggering current to the fuse link.

Abstract: A Schottky diode is presented which has reduced minority carrier injection and reduced diffusion of the metallization into the semiconductor. These improvements are obtained by interposing a layer comprising a mixture of silicon and chromium between the anode metallization layer and the semiconductor in a Schottky diode. The layer including chromium acts an effective barrier against the diffusion of the metallization layer into the semiconductor, and at the same time reduces the amount of minority carrier injection into the substrate. The layer including chromium requires no addition photolithograpic masks because it can be plasma etched using the metallization layer as a mask after that layer has been patterned.

Abstract: A circuit test of a semiconductor device having a redundant circuit for repairing defective circuit is carried with the fuse portion (21) of the redundant circuit and the bonding pad portion (26) exposed and the wiring layers (23) formed on the semiconductor substrate protected with a first protective layer (32). By this step, metal shavings (29) scraped from the surface of the bonding pad by a tester electrode terminal during the circuit test can be prevented from being directly in contact with the interconnection layers, whereby generation of short circuit can be prevented. Thereafter, the surfaces of the bonding pad portion and the fuse portion are covered with a second protective layer (33) and a third protective layer (25) (polyimide). The surface of the bonding pad portion is exposed by etching.

Abstract: The base-collector capacitance in a heterojunction bipolar transistor (HBT) (50) is reduced, thereby providing increased cutoff frequency and power gain, by eliminating a portion of a collector contact layer (54) which normally underlies a base electrode (66). A similar effect may be produced by forming the collector contact layer (54) such that it initially extends into the area (54c) under the base electrode (66), and subsequently rendering the collector contact layer (54) in this area (54c) semiinsulative by proton bombardment. A ballast resistor layer (70) is formed between an emitter layer (62) and an overlying emitter electrode (68) to prevent thermal runaway and hot spot formation. A plurality of the HBTs (50) may be arranged in a distributed amplifier configuration (80) including contact electrode bus lines (84,88) having a geometry designed to provide high thermal efficiency, and input and output circuit matching characteristics.

Abstract: A performance enhancing conductor (27) is employed to reduce a transistor's (10) on resistance and to also reduce the transistor's (10) parasitic gate to drain capacitance (32). The performance enhancing conductor (27) covers the transistor's (10) gate (22) and a portion of the drain region (18, 19) that is adjacent the transistor's channel (20). The performance enhancing conductor (27) is isolated from the gate (22) by an insulator (24, 26).

Abstract: A method for manufacturing an EEPROM comprises the step of using raw gas containing an organic compound having a molecular weight of more than 44, such as ethyl acetate and tetrahydrofuran when a first polysilicon layer serving as a select gate electrode and a second polysilicon layer serving as a floating gate electrode are deposited by a CVD process. The above described step allows a voltage at the time of tunneling electrons to be decreased.

Abstract: As semiconductor device includes a substrate and first and second semiconductor light receiving elements which are spaced apart and monolithically integrated on the substrate. The light receiving elements each has first and second terminals. A first flip-chip bonding pad is formed on the surface of the device and the device includes a first conductor element which electrically interconnects the first terminals of the elements in series and includes a centrally disposed portion that is electrically connected to the first flip-chip bonding pad. Second and third flip-chip bonding pads are also formed on a surface of the device and elongated electrodes are provided for electrically interconnecting the second terminal of the first light receiving element with the second flip-chip bonding pad and the second terminal of the second light receiving element with the third flip-chip bonding pad.

Abstract: A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current electrode (32) overlying the control electrode (28). MOS transistor (11) has a first current electrode (54) underlying a channel region (56), and a source lightly doped region (58) and a source heavily doped region (60) overlying the channel region (56). A control electrode conductive layer (40) is laterally adjacent a sidewall dielectric layer (48), and sidewall dielectric layer (48) is laterally adjacent channel region (56). Conductive layer (40) functions as a gate electrode for transistor (11). Each of the transistors (10 and 11) is vertically integrated such as in a vertically integrated BiMOS circuit. Transistors (10 and 11) can be electrically isolated by isolation ( 64 and 66).

Abstract: Lead frames, in which at least one part of the surface of a metal member which is a part of the lead frame is provided with an anodic oxide film of copper or a copper alloy, and in which a member composed substantially of a resin film or a resin plate is connected to the lead frame through this anodic oxide film by gluing or pressing under heat exhibit good adhesion between the metal member and the resin film or plate. Similarly, lead frames constructed with at least two metal members, having a portion of the surface provided with an anodic oxide film of copper or a copper alloy, and in which these metal members are joined together through this anodic oxide film exhibit good adhesion between the metal members.

Abstract: The invention relates to an integrated circuit having a vertical transistor. According to the invention, a transistor having a current amplification .beta. considerably higher than a conventional transistor is obtained due to the fact that the emitter (5) of the transistor has a thickness and a doping level such that the diffusion length of the minority charge carriers injected vertically into the latter is greater than or equal to the thickness of the emitter (5) and the emitter contact region is so small that during operation the total current of minority charge carriers injected from the base into the emitter region is much smaller than the current density of minority carriers injected from the base into the emitter region under the emitter contact region multiplied by the total surface area of the emitter region.

Abstract: A high density nonvolatilized semiconductor integrated circuit is comprised of a Dynamic RAM (DRAM) cell unit and a nonvolatile cell unit. The DRAM cell unit is comprised of a first transistor having its gate connected to a word line, its source connected to a bit line and its drain connected to a first capacitor. The first capacitor has its other electrode connected to a first line. The nonvolatile RAM cell unit is comprised of a second transistor having its gate connected to a second line, its source connected to the bit line and its drain connected to a second capacitor. The second capacitor has its other electrode connected to a third line. The second capacitor comprises a ferroelectric substance to which a reverse voltage is applied in order to read out its signal, and the first capacitor comprises a paraelectric substance to which such reverse voltage is not applied. The cycle life of the DRAM cell unit is thereby increased.

Abstract: An LED array in which the optical output distribution in each light emitting region is as uniform as possible. An n electrode 3 is provided on the under surface of a substrate 2 and a p electrode is provided on the upper surface thereof. A multiplicity of light emitting regions 4 are formed on the upper layer of the substrate 2. Two strip-like conductor portions 6c extending over each light emitting region 4 in ohmic contact are connected to each electrode 6 so that a current is efficiently applied to the conductor portions 6c of each light emitting region 4 and the optical output distribution in each light emitting region 4 is made uniform.

Abstract: A memory cell array (50) of a DRAM has a so-called divided bit line structure including two regions (50a and 50) divided from each other. One bit line (24) of a bit line pair is connected to a predetermined memory cell in a first memory cell array block (50a) and is kept in unloaded state in a second memory cell array block (50b). The other bit line (25) of a bit line pair is kept in unloaded state in the first memory cell array block (50a) and is connected to a predetermined memory cell in a first memory cell array block (50b). In these structures, the load state is kept same in both bit lines of the bit line pair. In the memory cell array, four memory cells are disposed in a cross-relationship, and are connected to the bit line (24) through a contact portion (17) used in common by the four memory cells. The word lines (20a and 20b) are formed to obliquely cross the bit lines and to extend perpendicularly to each other. Capacitors (3) in the memory cells have portions extended over the word lines.

Abstract: In a semiconductor device, an interconnection of differentially doped diffusion regions formed on a substrate includes an interconnecting layer disposed between the two diffusion regions so that the two regions are coupled to one another. The interconnect region is defined by the existing mask boundaries of N+ dopant and P+ dopant regions such that N+ and P+ dopant is not allowed to enter the interconnect region. Thus, the interconnect region is defined without requiring additional masking and etching steps. Once the interconnect region is defined, then the interconnecting layer is formed by a deposition and sintering process. The interconnecting layer provides a schottky barrier and ohmic contact.

Abstract: A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.

Abstract: A field effect transistor includes a GaAs substrate on which an undoped GaAs layer is disposed. A doped electron supply layer is disposed on the undoped GaAs layer and has a negligible deep dopant level. A channel layer disposed on the electron supply layer has a larger electron affinity than the electron supply layer. The electron supply layer and the channel layer form a heterojunction. A third semiconductor layer having the same conductivity type as the electron supply layer is disposed on the electron supply layer. Gate, drain, and source electrodes are disposed on the third semiconductor layer. The dopant concentration of the third layer is smaller than the dopant concentration of the electron supply layer.

Abstract: The invention relates to an integrated circuit connected via a first connection conductor (61) to a first contact area. Between the first connection conductor (61) and a second connection conductor (63), a protection element (8) is connected, which protects the circuit especially from electrostatic discharges. The protection element (8) comprises an active zone (81), which is covered with metal silicide (15) and forms a pn junction (86) with the adjoining part (83) of the semiconductor body (10). On the metal silicide (15), the active zone (81) is provided with an electrode (16), through which the zone (81) is connected to the first connection conductor (61). The use of metal silicide in the integrated circuit in itself has great advantages, but in the protection element the metal silicide layer is found to give rise to a considerably lower reliability. The invention has for its object to obviate this disadvantage without it being necessary to modify the manufacturing process.