Abstract: A diffused layer is formed in a semiconductor substrate in a connecting region wherein a word line and a shunt thereof are connected to each other, and the word line is also connected to the diffused layer. A junction breakdown voltage between the diffused layer and the semiconductor substrate is not higher than the breakdown voltage of a gate insulating film and is not lower than a maximum voltage applied during a burn-in operation. For this reason, charges accumulated in the word line during a wafer process are easily discharged to the semiconductor substrate through the diffused layer. In addition, since the diffused layer connected to the word line is formed in the connecting region wherein the word line and the shunt thereof are connected to each other, an additional region for the diffused layer is not required. Therefore, variations in characteristics of a transistor, or degradation and breakdown of the gate insulating film can be prevented without a decrease in integration density.

Abstract: A buried Zener diode has an auxiliary Zener junction access path in parallel with the force anode/cathode path. Unlike the force anode/cathode path, the auxiliary path is effectively by-passed by the current flowing between the force anode and cathode during circuit operation, so that there is no accumulation of significant resistance-current products that would otherwise mask the Zener voltage. The Zener diode has an anode region disposed in a first surface portion of a substrate. A `force` anode is formed on a first surface portion of the anode region. A `sense` anode is disposed on a second surface portion of the anode region spaced apart from the force anode. A first cathode region is disposed in a second surface portion of the substrate spaced apart from the anode region, while a sense cathode region is disposed in a third surface portion of the substrate spaced apart from each of the anode region and the first cathode region.

Abstract: An image sensing device that outputs a signal logarithmically proportional to the intensity of the incident light. The image sensing device makes use of a sub-threshold current flowing between the drain and source of a MOS transistor when the gate voltage is below the threshold voltage (above which the MOS transistor is nominally conductive and below which nominally non-conductive). Since the logarithmic conversion is done in the photosensing section of a solid-state image sensing device, the output from the device is already compressed and is easily handled by a small capacity CCD. Some output systems for the image sensing device of the present invention are also described.

Abstract: A semiconductor device includes a specific circuit portion having a predetermined function and a spare redundant circuit portion having the same function as the specific circuit portion. The semiconductor device includes a silicon substrate (1), an interlayer insulating film (2), an LT fuse (3), interconnection layers (4), a testing electrode (5) and a protection film (6). The interlayer insulating film (2) has a groove (11) and is formed on the silicon substrate (1). The LT fuse (3) is formed of polysilicon and is located immediately below the bottom wall of the groove (11). The interconnection layers (4) are formed on the interlayer insulating film (2) with the groove (11) therebetween. The testing electrode (5) is spaced from the interconnection layers (4) and is formed on the interlayer insulating film (2). The protection film (6) is formed on the interlayer insulating film to cover surfaces of the interconnection layers (4) and expose a surface of the testing electrode (5).

Abstract: The TFT structure formed in accordance with this invention includes a TFT body that has channel plug end sidewalls separated by a distance equal to or less than the width of the source/drain address lines and such that no residual doped semiconductor material adheres to the sidewalls. Similarly, the intrinsic semiconductor material layer is shaped such that no residual doped semiconductor material adheres to the sidewalls of the intrinsic semiconductor material layer underlying the channel plug ends.

Abstract: An integrated semiconductor device includes a pair of spaced apart regions of semiconductor material on a surface of a substrate of semiconductor material. One of the regions is a light emitting device and the other region is a light detector device. Each of the regions is formed of a first layer on the substrate surface of a composition suitable for serving as a light detector active layer. Additional layers are on the first layer with at least one of the additional layers being of a composition to act as a light emitter active layer. A contact layer may be provided on the additional layers. The light detector region has a highly conductive region extending through the additional layers and slightly into the light detector active layer. The light emitter region may have a highly conductive region extending through some of the additional layers to the light emitting active layer. Thus, both the light emitting region and the light detecting region are formed from the same layers of semiconductor material.

Abstract: A horizontal charge transfer register has an array of charge transfer sections for transferring signal charges in a charge transfer direction, the charge transfer sections including a final charge transfer section. A floating diffusion region is connected to the final charge transfer section through a horizontal output gate section. A pair of potential barrier regions or a potential well region extends from the final charge transfer section to the horizontal output gate section, for orienting an electric field in the charge transfer direction in the horizontal output gate section. The potential barrier regions are spaced from each other by a distance which is progressively smaller from the final charge transfer section toward the horizontal output gate section. The potential barrier regions define a charge transfer path therebetween which is substantially the same as or close to the width of the floating diffusion region.

Abstract: Construction method and apparatus for lightly doped drain MOSFET that has low or minimum drift on-state resistance and maintains high voltage blocking in the off-state. Temperature sensitivity of the electrical properties of the MOSFET are also reduced relative to MOSFETs produced by processes such as SIPOS. Voltage level shifting of p-channel and n-channel MOSFETs, produced according to the invention, relative to another voltage level is easily accomplished.

Abstract: A power semiconductor device is constructed by integrating a DMOS transistor and a lateral MOS transistor on the same semiconductor chip. The lateral MOS transistor is formed within a well with a conductivity type which is the same as the conductivity type of the source region of the DMOS transistor. The gate voltage is monitored at the time of connecting the gate and the drain of the lateral MOS transistor and of driving it at a constant current. When the gate voltage drops below a predetermined value, the driving of the DMOS transistor is stopped. The breakdown of the power semiconductor device due to heating can thus be prevented.

Abstract: A charge-coupled-device image sensor includes first, second and third linear array imagers, first, second and third horizontal charge-coupled-devices, first, second and third transfer gates and first and second vertically arranged charge-coupled-devices. The first transfer gate is operated so as to transfer electrons from the first linear array imager to the first horizontal charge-coupled-device. The third transfer gate, the first and second vertically arranged charge-coupled-devices and the second horizontal charge-coupled-device are operated so as to transfer electrons from the third linear array imager to the third horizontal charge-coupled-device. The second and third transfer gates and the first vertically arranged charge-coupled-device are operated after electrons from the third linear array imager have been transferred to the third horizontal charge-coupled-device so as to transfer electrons from the second linear array imager to the second horizontal charge-coupled-device.

Abstract: A solid-state charge-coupled-device imager has an imaging region composed of a matrix of vertically and horizontally arrayed photosensitive areas for storing signal charges depending on the intensity of applied light, and a plurality of vertical shift resisters for vertically transferring the signal charges shifted from the photosensitive areas. The signal charges from the vertical shift registers are shifted to a horizontal shift register that transfers the signal charges in a horizontal direction. The horizontal shift register comprises a plurality of charge transfer electrodes horizontally spaced at predetermined intervals. The charge transfer electrodes are inclined to the horizontal direction. The charge transfer electrodes may be inclined linearly in their entirety to the horizontal direction or may be of a chevron shape.

Abstract: A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the first region, the extrinsic base region generally bounding a portion of the first region; forming by ion implantation a linking region of the second conductivity type in the surface of the bounded portion of the first region so as to electrically link generally opposing edges of the extrinsic base region through the linking region; forming an insulating spacer over the junction between the extrinsic base region and the linking region so as to generally bound a portion of the linking region within the portion of the first region; etching the surface of the bounded portion of the linking region a short distance into the linking region; forming by epitaxial growth a first layer of semiconductor material of the second conductivity type on the etched surface of t

Abstract: A wide dynamic range photodetector comprising a photosensitive region for generating signal electrons in response to being illuminated, a collection region for storing the signal electrons generated within the photosensitive region, a shift register for receiving and outputing the signal electrons from the collection region, and a transfer gate intermediate the photosensitive region and the collection region for alternately facilitating transfer of the signal electrons from the photosensitive region for storage in the collection region, and isolating the photosensitive region from the collection region while the signal electrons are being output via the shift register.

Abstract: The present invention is directed to an image sensor which comprises a body of a semiconductor material having therein a plurality of photodetectors arranged in a line and a CCD shift register extending along the line of photodetectors adjacent to but spaced from an edge of the photodetectors. The CCD shift register includes a channel region and a plurality of first and second gate electrodes extending over and insulated from the channel region. One of each of the first and second gate electrodes extends across a portion of the edge of each photodetector. Each of the first electrodes has an arm extending along the entire edge of its respective photodetector between the photodetector and the second gate electrode. A separate transfer region is in the body between the edge of each photodetector and its respective first electrode and extends along the entire edge of the photodetector. A transfer gate is over and insulated from the transfer regions.

Abstract: Semiconductor package and method in which a cavity is provided for a chip or die, a bonding shelf extends peripherally of the cavity, and a layer of metallization extends along the under side of the shelf, wraps around the inner peripheral edge of the shelf and extends along the inner margin of the upper surface of the shelf to form a conductive ring to which a lead from the chip is bonded. Additional bonding pads are formed on the upper surface of the shelf, and additional leads from the chip are attached to these pads. In one embodiment, locating fingers align the chip precisely within the cavity.

Abstract: An image projection arrangement is disclosed, comprising a radiation source (1), an image display system having at least one image display panel (10) in which the polarisation direction of an incident beam is modulated with the image information, and a polarisation-sensitive beam splitter (2), arranged between the source and the image display system, for forming two mutually perpendicularly polarised sub-beams (b.sub.1, b.sub.2). By having the two sub-beams be modulated by the same image display system (10) and by thereafter combining these sub-beams again a very efficient use can be made of the available light without the necessity of a significant more complex design of the arrangement.

Abstract: An interline transfer type area image sensor which operates in a non-interlaced mode and has an array of columns and rows of photoreceptor in which charge from each pixel is transferred into a stage of a vertical two-phase CCD shift register formed by adjacent electrodes of the CCD. Each electrode of a stage has a separate voltage clock. An ion implanted vertical transfer barrier region is formed under an edge of each electrode.

Abstract: A method for producing a polarizer patterned with a plural number of portions having a polarizing ability or direction of polarization comprising the first step of producing a surface oriented in a pre-determined direction on a substrate, the second step of producing a polymerizable molecular layer which comprises polymerizable molecules on the above surface, the third step of polymerizing the molecules in said polymerizable molecular layer into a desired pattern and the fourth step of removing the unpolymerized portion of said polymerizable molecular layer.

Abstract: A semiconductor device comprises a semiconductor substrate, plural conductive lead circuit layers, one or more intermediate insulating layers interposed between the conductive lead circuit layers, and plural hole made in respective intermediate insulating layer. The hole has both a width larger than a width of the connection portion of the first conductive lead circuit layer positioned under the via and a depth that at a least a top face of the connection portion of the first conductive lead circuit layer is exposed, and a tungsten plug has a width layer than the width of the connection portion of the first conductive lead circuit layer, formed over at least the top face of the connection portion of the lower lead circuit layer 3. A gap between the conductive plug and the inner wall of the hole, is filled up with insulating material to form a flat surface on which the second conductive lead circuit layer is formed.

Abstract: A liquid crystal apparatus, includes: a) a liquid crystal device comprising an electrode matrix composed of scanning electrodes and data electrodes, and a ferroelectric liquid crystal showing a first and a second orientation state; and b) a driving means including: a first drive means for applying a scanning selection signal to the scanning electrodes two or more scanning electrodes apart in one vertical scanning so as to effect one picture scanning in plural times of vertical scanning, said scanning selection signal having a voltage of one polarity and a voltage of the other polarity with respect to the voltage level of a nonselected scanning electrode, and a second drive means for applying to a selected data electrode a voltage signal which provides a voltage causing the first orientation state of the ferroelectric liquid crystal in combination with the voltage of one polarity of the scanning selection signal, and applying to another data electrode a voltage signal which provides a voltage causing the secon