Patents Examined by Andrew Q. Tran
  • Method and solution for cleaning InGaAs (or III-V) substrates
    Patent number: 9905412
    Abstract: Embodiments described herein generally relate to improved methods and solutions for cleaning a substrate prior to epitaxial growth of Group III-V channel materials. A first processing gas, which includes a noble gas and a hydrogen source, is used to remove the native oxide layer from the substrate surface. A second processing gas, Ar/Cl2/H2, is then used to create a reactive surface layer on the substrate surface. Finally, a hydrogen bake with a third processing gas, which includes a hydrogen source and an arsine source, is used to remove the reactive layer from the substrate surface.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 27, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao
  • Mixtures, methods and compositions pertaining to conductive materials
    Patent number: 9902863
    Abstract: This invention pertains to mixtures and methods that can be used to produce materials comprising an electrically and/or thermally conductive coating as well as compositions that are materials that possess an electrically and/or thermally conductive coating. The mixtures and methods can be used to fabricate transparent conductive films and other transparent conductive materials.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: February 27, 2018
    Assignee: BASF SE
    Inventors: David Schultz, James Glass, Benjamin W. C. Garcia
  • Multi channel semiconductor device having multi dies and operation method thereof
    Patent number: 9899075
    Abstract: A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon-Joo Eom, Joon-Young Park, Yongcheol Bae, Won Young Lee, Seongjin Jang, Junghwan Choi, Joosun Choi
  • Pattern forming method capable of minimizing deviation of an inversion pattern
    Patent number: 9887099
    Abstract: A method includes: forming a metal oxide film on a substrate including an etching target film and a metal pattern formed thereon, and forming an oxide film having a relatively strong oxygen bond on the metal pattern; performing a reduction treatment such that the metal oxide film formed on the metal pattern is defined as a first metal-containing film and the metal oxide film formed on the etching target film is defined as a second metal-containing film whose surface is reduced into metal; selectively forming a metal film on only the second metal-containing film formed on the etching target film, the metal film having such a property that it is easy to be formed on metal and is hard to be formed on an oxide; and obtaining an inversion pattern composed of the inversion material by etching away the metal pattern and leaving the inversion material and the metal film.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 6, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroyuki Nagai
  • Coaxial connector feed-through for multi-level interconnected semiconductor wafers
    Patent number: 9887195
    Abstract: A semiconductor, silicon-on-oxide (SOI) structure having a silicon layer disposed on a bottom oxide (BOX) insulating layer. A deep trench isolation (DTI) material passes vertically through the silicon layer to the bottom oxide insulating layer. The deep trench isolation material has a lower permittivity than the permittivity of the silicon. A coaxial transmission line having an inner electrical conductor and an outer electrically conductive shield structure disposed around the inner electrical conductor passing vertically through the deep trench isolation material to electrically connect electrical conductors disposed over the bottom oxide insulating layer to electrical conductors disposed under the contacts bottom oxide insulating layer.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: February 6, 2018
    Assignee: Raytheon Company
    Inventors: John J. Drab, Mary A. Teshiba
  • Switched interface stacked-die memory architecture
    Patent number: 9875814
    Abstract: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 23, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Joe M. Jeddeloh, Paul A. LaBerge
  • Methods of forming contact holes using pillar masks and mask bridges
    Patent number: 9875932
    Abstract: A fabrication method of the semiconductor device comprises forming an isolation layer and an active region, which is defined by the isolation layer, on a substrate, forming an insulating layer on the substrate, forming a plurality of pillar masks, which are spaced from one another by a first gap and a second gap that is smaller than the first gap, on the insulating layer, forming spacers on the plurality of pillar masks, forming mask bridges in regions where the plurality of pillar masks are spaced from one another by the second gap by partially removing the spacers and forming a contact hole, which exposes the active region, by etching the insulating layer using the plurality of pillar masks and the mask bridges.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: January 23, 2018
    Assignee: Samsng Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Chan-Mi Lee
  • Sensing phase-change memory/test cells for determining whether a cell resistance has changed due to thermal exposure
    Patent number: 9875794
    Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: January 23, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jason Brand, Jason Snodgress
  • Stacked capacitor with enhanced capacitance and method of manufacturing the same
    Patent number: 9871095
    Abstract: A semiconductor device and method of manufacturing the same is provided. The semiconductor device includes a semiconductor substrate and a stacked capacitor. The stacked capacitor is over the semiconductor substrate. The stacked capacitor includes a lower electrode plate, an upper electrode plate, a dielectric layer, a cap layer, a first via hole and a second via hole. The lower electrode plate is over the semiconductor substrate. The upper electrode plate is over the lower electrode plate. The dielectric layer is between the lower electrode plate and the upper electrode plate. The cap layer is over the upper electrode plate. The first via hole is through the cap layer, the upper electrode plate and the dielectric layer, partially exposing the lower electrode plate. The second via hole is through the cap layer, partially exposing the upper electrode plate.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Szu-Yu Wang, Yeur-Luen Tu, Chih-Yu Lai
  • Circuit that selects EPROMs individually and in parallel
    Patent number: 9864524
    Abstract: An integrated circuit including a first EPROM, a second EPROM, and a circuit. The first EPROM is configured to provide a first state and a second state. The second EPROM is configured to provide a third state and a fourth state. The circuit is configured to select the first EPROM and the second EPROM individually and in parallel with each other.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 9, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ning Ge, Paul I. Mikulan, Bee Ling Peh
  • Photonic quantum memory with time-bin entangled photon storage
    Patent number: 9851742
    Abstract: A photonic quantum memory is provided. The photonic quantum memory includes entanglement basis conversion module configured to receive a first polarization-entangled photon pair and to produce a second entangled photon pair. The second polarization-entangled photon pair can he a time-bin entangled or a propagation direction-entangled photon pair. The photonic quantum memory further includes a photonic storage configured to receive the second entangled photon pair from the basis conversion module and to store the second entangled photon pair.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: December 26, 2017
    Assignee: The MITRE Corporation
    Inventors: Gerald N. Gilbert, Jonathan S. Hodges, Stephen Peter Pappas, Yaakov Shmuel Weinstein
  • Switchable macroscopic quantum state devices and methods for their operation
    Patent number: 9818479
    Abstract: Discloses is an electronic device and a method for its operation. The device has first and second electrodes and an active material. The active material has selectable and stable first and second macroscopic quantum states, such as charge density wave ordered states, having respectively first and second values of electrical resistivity ?1 and ?2 at the same temperature. ?1 is at least 2 times ?2. The method includes the step of switching between the first and second macroscopic quantum states by injection of current via the electrodes.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: November 14, 2017
    Assignee: JOZEF STEFAN INSTITUTE
    Inventors: Igor Vaskivskyi, Dragan D. Mihailović, Ian A. Mihailović
  • Circuit for adjusting a select gate voltage of a non-volatile memory during erasure of memory cells based on a well voltage
    Patent number: 9805803
    Abstract: A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, an adjustment unit, and a switch. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate. The switch is coupled in series with the adjustment unit between the select gate and the well.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: October 31, 2017
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Shuo-Nan Hung, Shin-Jang Shen, Wei-Jen Chen
  • Careless wiring substrate having an insulation layer with a bulged covering portion and semiconductor device thereof
    Patent number: 9799595
    Abstract: A wiring substrate is provided with a wiring pattern including a pad and a circuit pattern. The pad is formed in a mounting region where an electronic component is mounted, and the circuit pattern extends in a planar direction from the pad. An insulation layer covers a lower surface of the wiring pattern and a side surface of the wiring pattern and partially exposes an upper surface of the wiring pattern. The insulation layer includes a covering portion that continuously covers an entire peripheral portion of the upper surface of the wiring pattern. The insulation layer includes an upper surface located upward from the upper surface of the wiring pattern.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: October 24, 2017
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hiroshi Tomizawa, Katsuya Fukase
  • Static random access memory (SRAM) with recovery circuit for a write operation
    Patent number: 9799394
    Abstract: A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The first data line is electrically coupled with the memory cell array. The second data line is electrically coupled with the memory cell array. The driver circuit is electrically coupled with the first data line, the second data line and the third data line. The driver circuit includes a recovery circuit electrically coupled with the first data line, the second data line and the third data line. During a write operation of the SRAM, the recovery circuit is configured to pull a voltage level of the first data line to a first voltage level when the recovery circuit is enabled.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Wu, Kao-Cheng Lin, Wei Min Chan, Yen-Huei Chen
  • Nonvolatile memories having data input/output switches for reducing parasitic capacitance of bus channel
    Patent number: 9793000
    Abstract: A nonvolatile memory includes a memory cell array including a plurality of memory cells, a pad configured to be connected to a data input/output line, and an input/output circuit configured to receive data to be programmed in the memory cell array and to transmit data read from the memory cell array. The nonvolatile memory further includes a switch configured to couple and decouple the pad and the input/output circuit responsive to a switch control signal and a control circuit configured to generate the switch control signal responsive to a chip enable signal. Data storage devices and methods using such nonvolatile memories are also described.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: October 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jiwoon Park, Junghee Cho, Su-Jin Kim
  • Semiconductor memory device including refresh operations having first and second cycles
    Patent number: 9786352
    Abstract: Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: October 10, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Kenji Yoshida, Hiroki Fujisawa
  • Chip package method for reducing chip leakage current
    Patent number: 9786521
    Abstract: A chip package method can include: forming bonding pins on a first region of a first surface of a carrier; forming an insulating layer on an inactive face of a chip, where the inactive face of the chip is opposite to an active face of the chip; pasting the chip on a second region of the first surface of the carrier by the insulating layer; electrically coupling electrodes on the active face of the chip to the bonding pins by conductive wires; forming an enclosure to cover the chip and the bonding pins by a molding process; and peeling away the carrier from the enclosure to expose the bonding pins and the insulating layer on a surface of the enclosure.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: October 10, 2017
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Xiaochun Tan
  • Boosting channels of memory cells to reduce program disturb
    Patent number: 9779817
    Abstract: A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected memory string of the memory device, discharging the boosted channels of the memory cells in the selected memory string, and programming a selected memory cell in the selected memory string after discharging the boosted channels in the selected memory string.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Akira Goda, Mason A. Jones
  • Latching current sensing amplifier for memory array
    Patent number: 9779783
    Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Darren L. Anand, John A. Fifield, Eric D. Hunt-Schroeder, Mark D. Jacunski