Patents Examined by Andrew Q. Tran
  • Light emitting device excellent in color rendering property for emitting light closer to sunlight
    Patent number: 10134959
    Abstract: A light emitting device includes a first phosphor emitting a fluorescence having a peak emission wavelength of not less than 445 nm and not more than 490 nm, a second phosphor emitting a fluorescence having a peak emission wavelength of not less than 491 nm and not more than 600 nm, a third phosphor emitting a fluorescence having a peak emission wavelength of not less than 601 nm and not more than 670 nm, and a light emitting element that emits a light having a peak emission wavelength at a shorter wavelength side than the peak emission wavelength of the first phosphor. 0.586?x?0.734, 0.017?y?0.081, 0.239?z?0.384 and x+y+z=1 are satisfied, where x, y, z are defined as mass ratios of the first, second and third phosphors, respectively, to a total mass of the first, second and third phosphors.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 20, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Tomohiro Miwa, Shota Shimonishi, Shigeo Takeda, Satomi Seki, Daisuke Kato
  • Substrateless light emitting diode (LED) package for size shrinking and increased resolution of display device
    Patent number: 10134709
    Abstract: A light emitting diode package including a circuit layer, a light-shielding layer, a plurality of light emitting diodes and an encapsulation layer is provided. A thickness of the circuit layer is less than 100 ?m. The light-shielding layer is disposed on a first surface of the circuit layer and the light-shielding layer has a plurality of apertures. The light emitting diodes are disposed on the first surface of the circuit layer and in the apertures of the light-shielding layer. The light emitting diodes are electrically connected to the circuit layer. The encapsulation layer covers the light-shielding layer. A refractive index of the encapsulation layer is 1.4 and to 1.7. The Young's modulus of the encapsulation layer is larger than or equal to 1 GPa. A thickness of the encapsulation layer is greater than thicknesses of the light emitting diodes.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 20, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Hsien Wu, Yao-Jun Tsai, Chia-Hsin Chao, Yen-Hsiang Fang, Yi-Chen Lin, Ching-Ya Yeh
  • Semiconductor device
    Patent number: 10134838
    Abstract: A semiconductor device includes a substrate that includes active patterns extending in a second direction, a third device isolation layer disposed on an upper portion of the substrate that includes a PMOSFET region and an NMOSFET region, and a gate electrode that extends across the active patterns in a first direction that crosses the second direction. The active patterns extend across the PMOSFET region and the NMOSFET region. The third device isolation layer lies between the PMOSFET region and the NMOSFET region. The third device isolation layer comprises a first part that extends in the second direction and a second part that extends in a third direction that crosses the first and second directions. The second part has opposite sidewalls parallel to the third direction, in a plan view.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myoung-Ho Kang, Jung-Ho Do, Giyoung Yang, Seungyoung Lee
  • Recessed solid state apparatuses
    Patent number: 10134596
    Abstract: In some embodiments, an apparatus includes a first layer with a first surface and a second surface opposite to the first surface. The apparatus also includes a second layer having a third surface interfacing the second surface and a fourth surface opposite the third surface. The apparatus further includes a third layer having a fifth surface interfacing the fourth surface and a sixth surface opposite the fifth surface. The apparatus also includes a fourth layer having a seventh surface interfacing the sixth surface to form a heterojunction, which generates a two-dimensional electron gas channel formed in the fourth layer. Further, the apparatus includes a recess that extends from the first surface to the fifth surface.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dong Seup Lee, Yoshikazu Kondo, Pinghai Hao, Sameer Pendharkar
  • Integrated fan-out stacked package with fan-out redistribution layer (RDL)
    Patent number: 10128213
    Abstract: A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Hao-Yi Tsai, Tin-Hao Kuo
  • Leadframe strip with vertically offset die attach pads between adjacent vertical leadframe columns
    Patent number: 10115660
    Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: October 30, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Wei Fen Sueann Lim
  • Semiconductor device, MIM capacitor and associated fabricating method
    Patent number: 10115784
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a second dielectric layer over the first dielectric layer; an via extending through the second dielectric layer; a bottom conductive layer conformably formed at a bottom and along side walls of the via; a third dielectric layer conformably formed over the bottom conductive layer; an upper conductive layer conformably formed over the third dielectric layer; and an upper contact formed over and coupled to the upper conductive layer and filling the via; wherein the upper conductive layer provide a diffusion barrier between the upper contact and the third dielectric layer. A metal-insulator-metal (MIM) capacitor and an associated manufacturing method are also disclosed.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yen Chou, Shih-Chang Liu
  • Method for manufacturing wafer-level semiconductor packages
    Patent number: 10115579
    Abstract: During the manufacture of a semiconductor package, a semiconductor wafer including a plurality of bond pads on a surface of the wafer is provided and the surface of the wafer is covered with a dielectric material to form a dielectric layer over the bond pads. Portions of the dielectric layer corresponding to positions of the bond pads are removed to form a plurality of wells, wherein each well is configured to form a through-hole between top and bottom surfaces of the dielectric layer for exposing each bond pad. A conductive material is then deposited into the wells to form a conductive layer between the bond pads and a top surface of the dielectric layer. Thereafter, the semiconductor wafer is singulated to form a plurality of semiconductor packages.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 30, 2018
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Chun Ho Fan, Teng Hock Kuah
  • Fabrication method and structure of semiconductor device with contact and plug
    Patent number: 10109525
    Abstract: A method for fabricating a semiconductor device is provided including providing a substrate, on which a plurality of elements is formed. A first inter-dielectric layer is formed over the substrate, covering the elements. A first plug structure is formed in the first inter-dielectric layer, including performing a polishing process over the first inter-dielectric layer to have a dishing on top and extending from a sidewall of the first plug structure. A hard mask layer is formed to fill the dishing. A second inter-dielectric layer is formed over the hard mask layer. A second plug structure is formed in the second inter-dielectric layer to electrically contact the first plug structure, wherein the second plug structure has at least an edge portion extending on the hard mask layer.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 23, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Jiunn-Hsiung Liao, Wei-Hao Huang, Kai-Teng Cheng
  • Semiconductor structure having a bump lower than a substrate base and a width of the bump larger than a width of fin shaped structures, and manufacturing method thereof
    Patent number: 10109531
    Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A topmost portion of the first bump is lower than the base, and a width of the first bump is larger than a width of each of the fin shaped structures.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: October 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
  • System and method for depositing a homogenous interface for PECVD metal-doped carbon hardmasks
    Patent number: 10096475
    Abstract: A method for depositing a hardmask layer on a substrate includes nitridating a first layer of the substrate. The first layer is selected from a group consisting of silicon dioxide and silicon nitride. An amorphous carbon layer is deposited on the nitridated first layer via plasma-enhanced chemical vapor deposition (PECVD). A monolayer is deposited on the amorphous carbon layer using gas mixture including a metal precursor gas with a reducing agent and without plasma. A bulk metal-doped carbon hardmask layer is deposited on the monolayer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 9, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventor: Fayaz Shaikh
  • Memory device with buried word line for reduced gate-induced drain leakage current and method for manufacturing the same
    Patent number: 10083906
    Abstract: A memory device and a method for manufacturing a memory device are provided. The memory device includes a semiconductor substrate having a trench, an oxide layer formed on a surface of the trench, and a buried word line formed in the trench having the oxide layer formed thereon. The oxide layer includes a first portion extending downward from a top surface of the semiconductor substrate, a second portion extending upward from a bottom portion of the trench, and a third portion formed between and adjoining the first portion and the second portion. The third portion tapers toward the second portion. The first portion of the oxide layer is located between the buried word line and the surface of the trench.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 25, 2018
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Kai Jen, Wei-Che Chang, Kazutaka Manabe, Kazuaki Takesako, Noriaki Ikeda, Yoshinori Tanaka
  • Imaging apparatus with focus-ranging precision in one direction due to saturated photoelectric conversion elements located adjacent to each other
    Patent number: 10068940
    Abstract: An imaging apparatus includes a micro lens, a second photoelectric conversion element that is located adjacent to a first photoelectric conversion element in a first direction, and a third photoelectric conversion element that is located adjacent to the first photoelectric conversion in a second direction intersecting with the first direction, wherein the height of a potential barrier produced at a region between the first and third photoelectric conversion elements against a signal charge is less than the height of a potential barrier produced at a region between the first and second photoelectric conversion elements against a signal charge.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: September 4, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Satoshi Koizumi, Masahiro Kobayashi
  • Method of fabricating III-V fin structures and semiconductor device with III-V fin structures
    Patent number: 10062577
    Abstract: A method of fabricating III-V fin structures includes providing numerous fins. Then, a group III-V material layer is formed to encapsulate an upper portion of each of the fins. Later, part of the group III-V material layer is removed to expose an end of each of the fins, and divides the group III-V material layer into numerous U-shaped structures. Next, a first part of each of the fins and the entire silicon oxide layer are removed. Finally, part of each of the U-shaped structures is removed to segment each of the U-shaped structures into two III-V fin structures.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 28, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Wen Hung
  • Multi channel semiconductor device having multi dies and operation method thereof
    Patent number: 10062430
    Abstract: A multi channel semiconductor device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 28, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon-Joo Eom, Joon-Young Park, Yongcheol Bae, Won Young Lee, Seongjin Jang, Junghwan Choi, Joosun Choi
  • Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
    Patent number: 10049953
    Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Hao-Yi Tsai, Tin-Hao Kuo
  • Static random access memory (SRAM) using FinFETs with varying widths of fin structures
    Patent number: 10050043
    Abstract: In a method of manufacturing a semiconductor device, a first FinFET including a first fin structure, a first gate electrode structure disposed over the first fin structure and a first source/drain region is formed. A second FinFET including one second fin structure, a second gate electrode structure disposed over the second fin structure and a second source/drain region is formed. A first epitaxial layer is formed on the first fin structure in the first source/drain region, and a second epitaxial layer is formed on the second fin structure in the second source/drain region. A width of the first fin structure is smaller than a width of the second fin structure.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hung Hsieh, Jhon Jhy Liaw
  • Method for manufacturing a display device having an oxide semiconductor switching transistor
    Patent number: 10043424
    Abstract: It is an object to provide a specific driving method for reduction in power consumption in displaying a 3D image with field sequential driving.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Switched interface stacked-die memory architecture
    Patent number: 10037818
    Abstract: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 31, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Joe M. Jeddeloh, Paul A. LaBerge
  • Phase change memory with an incrementally ramped write-reference voltage and an incrementally ramped read-reference voltage
    Patent number: 10037802
    Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: July 31, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chung H. Lam, Scott C. Lewis, Thomas M. Maffitt, Jack Morrish