Patents Examined by Andrew Q. Tran
  • Process for producing a solar cell having an aromatic polyimide film substrate for high photoelectric conversion efficiency
    Patent number: 10217884
    Abstract: A CIS solar cell having flexibility and high conversion efficiency may be produced, using, as a substrate, a polyimide film which is prepared from an aromatic tetracarboxylic acid component comprising 3,3?,4,4?-biphenyltetracarboxylic dianhydride as the main component and an aromatic diamine component comprising p-phenylenediamine as the main component, and has a maximum dimensional change in the temperature-increasing step of from 25° C. to 500° C. within a range of from +0.6% to +0.9%, excluding +0.6%, based on the dimension at 25° C. before heat treatment.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: February 26, 2019
    Assignee: Ube Industries, Ltd.
    Inventors: Hiroaki Yamaguchi, Takao Miyamoto, Nobu Iizumi, Ken Kawagishi
  • Image sensor having shared pixel structure with symmetrical shape reset transistors and asymmetrical shape driver transistors
    Patent number: 10218927
    Abstract: An image sensor includes a pixel array including a plurality of pixel blocks, each including a light receiving section including unit pixels which share a floating diffusion; a first driving section disposed at one side of the light receiving section and including a reset transistor; and a second driving section disposed adjacent to the first driving section and including a driver transistor, wherein the pixel blocks include a first pixel block and a second pixel block which is adjacent to the first pixel block, and, with respect to a boundary where the first pixel block and the second pixel adjoin each other, the first driving section of the first pixel block has a shape symmetrical to the first driving section of the second pixel block and the second driving section of the first pixel block has a shape asymmetrical to the second driving section of the second pixel block.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: February 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Pyong-Su Kwag, Hye-Won Mun
  • Fin patterns with varying spacing without fin cut
    Patent number: 10217634
    Abstract: Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using a directional deposition process. A finless region is masked by forming a mask on a second sidewall of one or more of the plurality of mandrels. Second spacers are formed on a second sidewall of unmasked mandrels using a directional deposition process. The finless region is unmasked and each of the plurality of mandrels is etched away. Fins are formed from a substrate using the first and second spacers as a mask, such that no fins are formed in the finless region.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, John R. Sporre, Sean Teehan
  • Integrated circuit sensor device for charge detection hybridizing a lateral metal oxide semiconductor field effect transistor (MOSFET) and a vertical bipolar junction transistor (BJT)
    Patent number: 10209215
    Abstract: A semiconductor based integrated sensor device includes: a lateral insulating-gate field effect transistor (MOSFET) connected in series to the base of a vertical bipolar junction transistor (BJT) wherein the drain-drift-region of the MOSFET is part of the base-region of the BJT within the semiconductor substrate thus making electrical contact to the base of the BJT and the distance of the drain-drift-region of the MOSFET to the emitter of the BJT exceeds the vertical distance between the emitter and any buried layer, serving as collector, and the breakdown voltage of the device being determined by the BVCEO of the vertical BJT.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: February 19, 2019
    Assignee: K.EKLUND INNOVATION
    Inventors: Klas-Hakan Eklund, Shili Zhang, Ulf Smith, Hans Erik Norstrom
  • Fin patterns with varying spacing without fin cut
    Patent number: 10211055
    Abstract: Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of multiple mandrels using an angled deposition process. A second sidewall of one or more of the mandrels is masked in a finless region. Second spacers are formed on a second sidewall of all unmasked mandrels. Semiconductor fins are formed from a substrate using the first and second spacers as a pattern mask.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, John R. Sporre, Sean Teehan
  • Thin-film transistor, manufacturing method for the same, display panel
    Patent number: 10205028
    Abstract: A thin-film transistor, a manufacturing for the same, and a display panel are provided. In the annealing process, the aluminum layer combines with oxygen ions in the amorphous oxide semiconductor layer to form an Al2O3 layer. The amorphous oxide semiconductor layer loses the oxygen ions, oxygen defects are increased such that a doped region of the semiconductor layer is formed. That is, a source contact region and a drain contact region are formed, and the amorphous oxide semiconductor layer is shielded by the anti-oxidation layer to form the channel region of the semiconductor layer. The present invention can simplify the manufacturing process, increase the production efficiency and decrease the production cost.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: February 12, 2019
    Assignee: Shenzhen China Star Optoelectroncis Semiconductor Display Technology Co., Ltd
    Inventor: Longqiang Shi
  • High voltage withstand Ga2O3-based single crystal schottky barrier diode
    Patent number: 10199512
    Abstract: A high withstand voltage Schottky barrier diode includes a first layer that includes a first Ga2O3-based single crystal including a first Group IV element and Cl at a concentration of not more than 5×1016 cm?3 and that has an effective donor concentration of not less than 1×1013 and not more than 6.0×1017 cm?3, a second layer that includes a second Ga2O3-based single crystal including a second Group IV element and that has a higher effective donor concentration than the first layer and is laminated on the first layer, an anode electrode formed on the first layer, and a cathode electrode formed on the second layer.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 5, 2019
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Kohei Sasaki, Ken Goto, Masataka Higashiwaki, Akinori Koukitu, Yoshinao Kumagai, Hisashi Murakami
  • Antifuse unit cell of nonvolatile memory device for enhancing data sense margin and nonvolatile memory device with the same
    Patent number: 10199117
    Abstract: Disclosed are a unit cell capable of improving a reliability by enhancing a data sensing margin in a read operation, and a nonvolatile memory device with the same. The unit cell of a nonvolatile memory device includes: an antifuse having a first terminal between an input terminal and an output terminal; and a first switching unit coupled between a second terminal of the antifuse and a ground voltage terminal.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: February 5, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Chang-Hee Shin, Ki-Seok Cho, Seong-Do Jeon, Youn-Jang Kim
  • Silicon carbide (SiC) MOSFET with a silicon oxide layer capable of suppressing deterioration of carrier mobility and variation in threshold voltage
    Patent number: 10186596
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer, a gate electrode, and a silicon oxide layer disposed between the silicon carbide layer and the gate electrode, a number of single bonds between carbon atoms being larger than that of double bonds between carbon atoms in the silicon oxide layer.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: January 22, 2019
    Assignees: Kabushiki Kaisha Toshiba, National Institute for Materials Science
    Inventors: Tatsuo Shimizu, Takahisa Ohno, Tomoaki Kaneko, Takahiro Yamasaki, Nobuo Tajima, Jun Nara
  • Tamper resistant electronic hardware assembly with a non-functional die used as a protective layer
    Patent number: 10181430
    Abstract: An electronic hardware assembly including at least a first and second laminar component, wherein the first laminar components includes a die, the die including a substrate, a functional region and a first protective layer, and the second laminar component includes a second protective layer, wherein the first and second laminar components are arranged in a stack such that the functional region of the first laminar component is arranged within the assembly substantially between first and second protective layers.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: January 15, 2019
    Assignee: QINETIQ LIMITED
    Inventors: Nigel Clement Davies, David John Lees
  • Method of manufacturing a static random access memory (SRAM) using FinFETs with varying widths of fin structures
    Patent number: 10177158
    Abstract: In a method of manufacturing a semiconductor device, a first fin structure, a second fin structure and a third fin structure, which extend in a first direction, are formed over a substrate. A first gate structure is formed over the first to third fin structures. The first gate structure extends in a second direction crossing the first direction. The first fin structure and the second fin structure are arranged adjacent to each other, and widths of the first and second fin structures in the second direction are smaller than a width of the third fin structure in the second direction.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hung Hsieh, Jhon Jhy Liaw
  • Method for forming an extremely thin silicon-on-insulator (ETSOI) device having reduced parasitic capacitance and contact resistance due to wrap-around structure of source/drain regions
    Patent number: 10170628
    Abstract: A method for forming a semiconductor device includes etching a semiconductor layer using a gate structure and spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure. Undercuts are formed in a buried dielectric layer under the gate structure. Source and drain regions are epitaxially growing and wrapped around the semiconductor layer by forming the source and drain regions adjacent to the gate structure on a first side of the semiconductor layer and in the undercuts on a second side of the semiconductor layer opposite the first side.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Stacked capacitor with enhanced capacitance
    Patent number: 10170539
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a stacked structure and contact vias. The stacked structure includes a plurality of conductive layers, and two adjacent conductive layers are isolated from each other with at least one dielectric layer. The contact vias have different heights, and partially through the stacked structure. Each of the plurality of contact vias is electrically connected to a corresponding conductive layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Szu-Yu Wang, Yeur-Luen Tu, Chih-Yu Lai
  • Method of storing and retrieving data for a resistive random access memory (RRAM) array with multi-memory cells per bit
    Patent number: 10170183
    Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Adam Johnson
  • Device having substrate with conductive pillars
    Patent number: 10163812
    Abstract: A device includes a substrate that includes conductive structures and has a first surface that is opposite to a second surface. Conductive pillars are built up over and electrically coupled to at least one of the conductive structures. An integrated circuit is disposed over the first surface and electrically coupled to the conductive structures. A molding compound is formed over the first surface of the substrate.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: December 25, 2018
    Assignee: Infineon Technologies AG
    Inventors: Chau Fatt Chiang, Kok Yau Chua, Swee Kah Lee, Chee Yang Ng, Valentyn Solomko
  • Deep trench capacitor with a filled trench and a doped region serving as a capacitor electrode
    Patent number: 10164005
    Abstract: The present disclosure provides a semiconductor structure which comprises a semiconductive substrate and a doped region in the semiconductive substrate. The doped region has a conductivity type opposite to the semiconductive substrate. The semiconductor structure also includes a capacitor in the doped region where the capacitor comprises a plurality of electrodes and the plurality of electrodes are insulated with one another. The semiconductor structure further includes a plug in the capacitor and surrounded by the plurality of electrodes.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Felix Ying-Kit Tsui, Shih-Fen Huang
  • Resistive random access memory having multi-cell memory bits
    Patent number: 10157673
    Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Adam Johnson
  • Method of storing and retrieving information for a resistive random access memory (RRAM) with multi-memory cells per bit
    Patent number: 10157669
    Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Adam Johnson
  • Methods and solutions for cleaning INGAAS (or III-V) substrates
    Patent number: 10147596
    Abstract: Embodiments described herein generally relate to improved methods and solutions for cleaning a substrate prior to epitaxial growth of Group III-V channel materials. A first processing gas, which includes a noble gas and a hydrogen source, is used to remove the native oxide layer from the substrate surface. A second processing gas, Ar/Cl2/H2, is then used to create a reactive surface layer on the substrate surface. Finally, a hydrogen bake with a third processing gas, which includes a hydrogen source and an arsine source, is used to remove the reactive layer from the substrate surface.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: December 4, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao
  • Wafer-level packaging sensing device and method for forming the same
    Patent number: 10140498
    Abstract: A method for forming a sensing device includes providing a first substrate. The first substrate has a first surface and a second surface opposite thereto. A sensing region is adjacent to the first surface. A temporary cover plate is provided on the second surface to cover the sensing region. The method also includes forming a redistribution layer on the second surface and electrically connected to the sensing region. The method further includes removing the temporary cover plate after the formation of the redistribution layer. The first substrate is bonded to a second substrate and a cover plate after the removal of the temporary cover plate so that the first substrate is positioned between the second substrate and the cover plate. In addition, the method includes filling an encapsulating layer between the second substrate and the cover plate to surround the first substrate.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: November 27, 2018
    Assignee: XINTEC INC.
    Inventors: Tsang-Yu Liu, Ying-Nan Wen, Chi-Chang Liao, Yu-Lung Huang